Module Definition
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Module : tm28hpcp_dlyc_d4_l35
SCORELINECONDTOGGLEFSMBRANCHASSERT
50.00 50.00 50.00 50.00

Source File(s) :
/nfs_project/gemini/DV/baber/gemini/design/ip/dti/libs/dti_tm28hpcp_ddr4_phy/hdl/library/tm28hpcp_dlyc_d4_l35.v

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2212.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2212.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2212.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2212.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2212.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2212.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2212.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2212.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2212.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2212.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2212.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2212.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2212.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2212.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2212.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2212.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2212.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2212.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2212.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2212.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2212.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2212.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2212.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2212.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2212.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2212.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2212.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2212.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2212.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2212.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2212.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2212.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2212.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4943.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4943.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4943.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4943.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4943.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4943.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4943.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4943.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4943.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4943.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4943.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4943.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4943.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4943.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4943.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4943.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4943.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4943.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4943.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4943.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4943.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4943.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4943.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4943.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4943.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4943.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4943.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4943.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4943.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4943.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4943.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4943.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4943.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4980.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4980.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4980.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4980.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4980.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4980.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4980.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4980.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4980.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4980.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4980.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4980.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4980.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4980.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4980.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4980.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4980.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4980.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4980.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4980.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4980.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4980.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4980.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4980.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4980.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4980.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4980.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4980.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4980.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4980.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4980.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4980.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4980.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6144.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6144.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6144.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6144.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6144.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6144.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6144.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6144.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6144.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6144.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6144.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6144.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6144.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6144.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6144.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6144.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6144.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6144.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6144.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6144.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6144.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6144.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6144.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6144.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6144.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6144.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6144.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6144.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6144.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6144.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6144.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6144.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6144.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8128.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8128.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8128.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8128.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8128.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8128.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8128.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8128.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8128.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8128.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8128.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8128.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8128.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8128.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8128.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8128.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8128.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8128.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8128.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8128.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8128.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8128.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8128.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8128.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8128.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8128.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8128.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8128.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8128.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8128.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8128.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8128.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8128.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8183.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8183.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8183.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8183.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8183.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8183.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8183.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8183.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8183.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8183.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8183.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8183.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8183.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8183.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8183.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8183.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8183.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8183.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8183.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8183.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8183.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8183.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8183.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8183.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8183.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8183.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8183.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8183.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8183.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8183.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8183.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8183.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8183.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8599.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8599.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8599.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8599.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8599.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8599.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8599.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8599.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8599.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8599.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8599.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8599.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8599.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8599.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8599.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8599.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8599.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8599.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8599.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8599.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8599.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8599.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8599.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8599.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8599.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8599.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8599.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8599.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8599.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8599.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8599.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8599.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8599.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9154.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9154.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9154.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9154.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9154.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9154.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9154.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9154.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9154.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9154.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9154.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9154.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9154.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9154.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9154.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9154.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9154.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9154.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9154.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9154.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9154.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9154.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9154.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9154.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9154.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9154.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9154.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9154.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9154.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9154.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9154.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9154.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9154.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10450.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10450.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10450.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10450.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10450.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10450.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10450.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10450.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10450.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10450.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10450.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10450.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10450.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10450.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10450.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10450.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10450.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10450.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10450.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10450.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10450.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10450.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10450.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10450.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10450.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10450.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10450.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10450.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10450.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10450.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10450.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10450.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10450.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11399.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11399.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11399.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11399.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11399.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11399.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11399.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11399.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11399.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11399.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11399.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11399.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11399.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11399.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11399.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11399.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11399.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11399.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11399.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11399.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11399.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11399.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11399.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11399.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11399.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11399.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11399.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11399.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11399.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11399.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11399.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11399.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11399.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11468.xdly.x1i27 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11468.xdly.x1i28 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11468.xdly.x1i29 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11468.xdly.x1i30 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11468.xdly.x1i31 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11468.xdly.x1i36 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11468.xdly.x1i40 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11468.xdly.x1i45 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11468.xdly.x1i49 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11468.xdly.x1i50 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11468.xdly.x1i51 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11468.xdly.x1i80 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11468.xdly.x1i81 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11468.xdly.x1i82 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11468.xdly.x1i83 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11468.xdly.x1i84 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11468.xdly.x1i85 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11468.xdly.x1i89 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11468.xdly.x1i93 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11468.xdly.x1i96 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11468.xdly.x1i103 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11468.xdly.x1i108 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11468.xdly.x1i112 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11468.xdly.x1i117 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11468.xdly.x1i120 41.67 50.00 25.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11468.xdly.x1i121 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11468.xdly.x1i122 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11468.xdly.x1i123 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11468.xdly.x1i175 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11468.xdly.x1i177 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11468.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11468.xdly.x1i193 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11468.xdly.xfc.x3 45.83 50.00 37.50 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11821.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11821.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11821.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11821.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11821.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11821.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11821.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11821.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11821.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11821.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11821.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11821.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11821.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11821.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11821.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11821.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11821.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11821.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11821.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11821.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11821.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11821.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11821.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11821.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11821.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11821.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11821.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11821.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11821.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11821.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11821.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11821.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11821.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12338.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12338.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12338.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12338.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12338.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12338.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12338.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12338.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12338.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12338.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12338.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12338.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12338.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12338.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12338.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12338.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12338.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12338.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12338.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12338.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12338.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12338.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12338.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12338.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12338.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12338.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12338.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12338.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12338.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12338.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12338.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12338.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12338.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12549.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12549.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12549.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12549.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12549.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12549.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12549.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12549.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12549.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12549.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12549.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12549.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12549.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12549.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12549.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12549.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12549.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12549.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12549.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12549.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12549.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12549.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12549.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12549.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12549.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12549.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12549.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12549.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12549.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12549.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12549.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12549.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12549.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14901.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14901.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14901.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14901.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14901.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14901.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14901.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14901.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14901.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14901.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14901.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14901.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14901.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14901.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14901.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14901.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14901.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14901.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14901.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14901.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14901.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14901.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14901.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14901.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14901.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14901.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14901.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14901.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14901.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14901.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14901.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14901.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14901.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18404.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18404.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18404.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18404.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18404.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18404.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18404.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18404.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18404.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18404.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18404.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18404.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18404.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18404.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18404.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18404.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18404.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18404.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18404.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18404.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18404.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18404.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18404.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18404.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18404.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18404.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18404.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18404.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18404.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18404.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18404.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18404.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18404.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20434.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20434.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20434.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20434.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20434.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20434.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20434.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20434.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20434.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20434.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20434.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20434.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20434.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20434.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20434.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20434.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20434.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20434.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20434.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20434.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20434.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20434.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20434.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20434.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20434.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20434.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20434.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20434.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20434.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20434.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20434.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20434.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20434.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21118.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21118.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21118.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21118.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21118.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21118.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21118.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21118.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21118.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21118.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21118.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21118.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21118.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21118.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21118.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21118.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21118.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21118.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21118.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21118.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21118.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21118.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21118.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21118.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21118.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21118.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21118.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21118.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21118.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21118.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21118.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21118.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21118.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22684.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22684.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22684.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22684.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22684.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22684.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22684.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22684.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22684.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22684.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22684.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22684.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22684.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22684.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22684.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22684.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22684.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22684.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22684.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22684.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22684.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22684.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22684.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22684.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22684.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22684.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22684.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22684.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22684.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22684.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22684.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22684.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22684.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23103.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23103.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23103.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23103.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23103.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23103.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23103.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23103.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23103.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23103.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23103.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23103.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23103.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23103.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23103.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23103.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23103.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23103.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23103.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23103.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23103.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23103.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23103.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23103.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23103.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23103.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23103.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23103.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23103.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23103.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23103.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23103.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23103.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23403.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23403.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23403.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23403.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23403.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23403.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23403.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23403.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23403.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23403.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23403.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23403.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23403.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23403.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23403.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23403.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23403.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23403.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23403.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23403.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23403.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23403.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23403.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23403.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23403.xdly.x1i120 4.17 0.00 12.50 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23403.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23403.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23403.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23403.xdly.x1i175 8.33 0.00 25.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23403.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23403.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23403.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23403.xdly.xfc.x3 45.83 50.00 37.50 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23498.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23498.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23498.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23498.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23498.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23498.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23498.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23498.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23498.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23498.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23498.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23498.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23498.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23498.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23498.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23498.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23498.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23498.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23498.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23498.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23498.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23498.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23498.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23498.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23498.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23498.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23498.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23498.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23498.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23498.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23498.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23498.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23498.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25011.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25011.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25011.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25011.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25011.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25011.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25011.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25011.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25011.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25011.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25011.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25011.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25011.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25011.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25011.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25011.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25011.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25011.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25011.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25011.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25011.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25011.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25011.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25011.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25011.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25011.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25011.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25011.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25011.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25011.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25011.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25011.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25011.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26871.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26871.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26871.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26871.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26871.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26871.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26871.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26871.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26871.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26871.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26871.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26871.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26871.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26871.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26871.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26871.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26871.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26871.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26871.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26871.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26871.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26871.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26871.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26871.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26871.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26871.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26871.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26871.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26871.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26871.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26871.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26871.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26871.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27051.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27051.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27051.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27051.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27051.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27051.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27051.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27051.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27051.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27051.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27051.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27051.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27051.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27051.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27051.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27051.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27051.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27051.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27051.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27051.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27051.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27051.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27051.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27051.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27051.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27051.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27051.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27051.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27051.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27051.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27051.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27051.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27051.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27508.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27508.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27508.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27508.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27508.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27508.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27508.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27508.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27508.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27508.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27508.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27508.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27508.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27508.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27508.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27508.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27508.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27508.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27508.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27508.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27508.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27508.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27508.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27508.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27508.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27508.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27508.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27508.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27508.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27508.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27508.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27508.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27508.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28218.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28218.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28218.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28218.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28218.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28218.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28218.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28218.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28218.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28218.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28218.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28218.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28218.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28218.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28218.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28218.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28218.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28218.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28218.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28218.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28218.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28218.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28218.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28218.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28218.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28218.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28218.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28218.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28218.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28218.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28218.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28218.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28218.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28973.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28973.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28973.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28973.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28973.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28973.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28973.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28973.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28973.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28973.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28973.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28973.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28973.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28973.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28973.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28973.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28973.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28973.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28973.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28973.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28973.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28973.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28973.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28973.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28973.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28973.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28973.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28973.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28973.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28973.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28973.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28973.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28973.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29802.xdly.x1i27 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29802.xdly.x1i28 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29802.xdly.x1i29 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29802.xdly.x1i30 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29802.xdly.x1i31 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29802.xdly.x1i36 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29802.xdly.x1i40 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29802.xdly.x1i45 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29802.xdly.x1i49 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29802.xdly.x1i50 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29802.xdly.x1i51 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29802.xdly.x1i80 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29802.xdly.x1i81 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29802.xdly.x1i82 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29802.xdly.x1i83 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29802.xdly.x1i84 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29802.xdly.x1i85 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29802.xdly.x1i89 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29802.xdly.x1i93 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29802.xdly.x1i96 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29802.xdly.x1i103 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29802.xdly.x1i108 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29802.xdly.x1i112 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29802.xdly.x1i117 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29802.xdly.x1i120 41.67 50.00 25.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29802.xdly.x1i121 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29802.xdly.x1i122 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29802.xdly.x1i123 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29802.xdly.x1i175 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29802.xdly.x1i177 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29802.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29802.xdly.x1i193 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29802.xdly.xfc.x3 45.83 50.00 37.50 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst89.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst89.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst89.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst89.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst89.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst89.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst89.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst89.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst89.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst89.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst89.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst89.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst89.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst89.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst89.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst89.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst89.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst89.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst89.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst89.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst89.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst89.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst89.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst89.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst89.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst89.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst89.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst89.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst89.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst89.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst89.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst89.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst89.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst254.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst254.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst254.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst254.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst254.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst254.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst254.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst254.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst254.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst254.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst254.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst254.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst254.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst254.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst254.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst254.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst254.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst254.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst254.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst254.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst254.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst254.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst254.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst254.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst254.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst254.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst254.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst254.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst254.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst254.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst254.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst254.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst254.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst382.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst382.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst382.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst382.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst382.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst382.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst382.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst382.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst382.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst382.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst382.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst382.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst382.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst382.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst382.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst382.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst382.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst382.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst382.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst382.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst382.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst382.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst382.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst382.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst382.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst382.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst382.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst382.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst382.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst382.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst382.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst382.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst382.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst401.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst401.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst401.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst401.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst401.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst401.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst401.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst401.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst401.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst401.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst401.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst401.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst401.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst401.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst401.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst401.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst401.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst401.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst401.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst401.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst401.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst401.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst401.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst401.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst401.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst401.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst401.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst401.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst401.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst401.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst401.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst401.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst401.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31343.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31343.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31343.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31343.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31343.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31343.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31343.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31343.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31343.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31343.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31343.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31343.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31343.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31343.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31343.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31343.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31343.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31343.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31343.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31343.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31343.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31343.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31343.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31343.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31343.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31343.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31343.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31343.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31343.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31343.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31343.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31343.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31343.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31524.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31524.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31524.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31524.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31524.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31524.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31524.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31524.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31524.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31524.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31524.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31524.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31524.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31524.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31524.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31524.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31524.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31524.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31524.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31524.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31524.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31524.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31524.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31524.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31524.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31524.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31524.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31524.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31524.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31524.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31524.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31524.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31524.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32144.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32144.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32144.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32144.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32144.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32144.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32144.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32144.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32144.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32144.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32144.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32144.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32144.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32144.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32144.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32144.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32144.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32144.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32144.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32144.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32144.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32144.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32144.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32144.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32144.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32144.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32144.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32144.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32144.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32144.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32144.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32144.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32144.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32215.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32215.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32215.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32215.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32215.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32215.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32215.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32215.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32215.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32215.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32215.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32215.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32215.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32215.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32215.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32215.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32215.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32215.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32215.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32215.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32215.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32215.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32215.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32215.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32215.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32215.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32215.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32215.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32215.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32215.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32215.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32215.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32215.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33607.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33607.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33607.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33607.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33607.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33607.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33607.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33607.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33607.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33607.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33607.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33607.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33607.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33607.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33607.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33607.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33607.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33607.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33607.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33607.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33607.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33607.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33607.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33607.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33607.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33607.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33607.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33607.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33607.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33607.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33607.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33607.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33607.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst100.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst100.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst100.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst100.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst100.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst100.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst100.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst100.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst100.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst100.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst100.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst100.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst100.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst100.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst100.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst100.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst100.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst100.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst100.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst100.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst100.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst100.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst100.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst100.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst100.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst100.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst100.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst100.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst100.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst100.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst100.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst100.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst100.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst89.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst89.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst89.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst89.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst89.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst89.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst89.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst89.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst89.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst89.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst89.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst89.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst89.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst89.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst89.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst89.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst89.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst89.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst89.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst89.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst89.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst89.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst89.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst89.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst89.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst89.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst89.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst89.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst89.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst89.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst89.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst89.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst89.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst254.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst254.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst254.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst254.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst254.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst254.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst254.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst254.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst254.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst254.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst254.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst254.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst254.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst254.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst254.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst254.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst254.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst254.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst254.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst254.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst254.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst254.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst254.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst254.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst254.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst254.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst254.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst254.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst254.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst254.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst254.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst254.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst254.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst382.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst382.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst382.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst382.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst382.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst382.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst382.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst382.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst382.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst382.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst382.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst382.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst382.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst382.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst382.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst382.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst382.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst382.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst382.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst382.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst382.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst382.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst382.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst382.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst382.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst382.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst382.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst382.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst382.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst382.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst382.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst382.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst382.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst401.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst401.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst401.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst401.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst401.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst401.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst401.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst401.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst401.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst401.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst401.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst401.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst401.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst401.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst401.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst401.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst401.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst401.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst401.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst401.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst401.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst401.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst401.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst401.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst401.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst401.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst401.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst401.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst401.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst401.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst401.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst401.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst401.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1046.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1046.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1046.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1046.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1046.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1046.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1046.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1046.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1046.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1046.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1046.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1046.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1046.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1046.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1046.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1046.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1046.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1046.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1046.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1046.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1046.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1046.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1046.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1046.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1046.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1046.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1046.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1046.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1046.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1046.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1046.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1046.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1046.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1394.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1394.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1394.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1394.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1394.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1394.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1394.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1394.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1394.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1394.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1394.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1394.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1394.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1394.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1394.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1394.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1394.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1394.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1394.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1394.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1394.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1394.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1394.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1394.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1394.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1394.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1394.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1394.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1394.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1394.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1394.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1394.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1394.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1629.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1629.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1629.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1629.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1629.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1629.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1629.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1629.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1629.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1629.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1629.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1629.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1629.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1629.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1629.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1629.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1629.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1629.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1629.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1629.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1629.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1629.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1629.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1629.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1629.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1629.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1629.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1629.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1629.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1629.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1629.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1629.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1629.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1862.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1862.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1862.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1862.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1862.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1862.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1862.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1862.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1862.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1862.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1862.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1862.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1862.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1862.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1862.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1862.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1862.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1862.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1862.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1862.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1862.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1862.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1862.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1862.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1862.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1862.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1862.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1862.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1862.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1862.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1862.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1862.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1862.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2210.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2210.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2210.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2210.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2210.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2210.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2210.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2210.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2210.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2210.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2210.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2210.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2210.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2210.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2210.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2210.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2210.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2210.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2210.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2210.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2210.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2210.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2210.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2210.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2210.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2210.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2210.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2210.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2210.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2210.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2210.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2210.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2210.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2250.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2250.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2250.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2250.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2250.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2250.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2250.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2250.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2250.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2250.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2250.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2250.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2250.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2250.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2250.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2250.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2250.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2250.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2250.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2250.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2250.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2250.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2250.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2250.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2250.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2250.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2250.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2250.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2250.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2250.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2250.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2250.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2250.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2461.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2461.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2461.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2461.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2461.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2461.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2461.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2461.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2461.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2461.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2461.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2461.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2461.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2461.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2461.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2461.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2461.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2461.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2461.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2461.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2461.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2461.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2461.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2461.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2461.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2461.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2461.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2461.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2461.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2461.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2461.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2461.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2461.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2711.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2711.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2711.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2711.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2711.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2711.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2711.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2711.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2711.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2711.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2711.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2711.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2711.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2711.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2711.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2711.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2711.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2711.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2711.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2711.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2711.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2711.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2711.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2711.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2711.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2711.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2711.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2711.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2711.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2711.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2711.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2711.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2711.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2731.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2731.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2731.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2731.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2731.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2731.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2731.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2731.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2731.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2731.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2731.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2731.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2731.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2731.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2731.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2731.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2731.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2731.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2731.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2731.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2731.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2731.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2731.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2731.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2731.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2731.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2731.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2731.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2731.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2731.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2731.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2731.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2731.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3889.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3889.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3889.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3889.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3889.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3889.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3889.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3889.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3889.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3889.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3889.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3889.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3889.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3889.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3889.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3889.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3889.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3889.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3889.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3889.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3889.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3889.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3889.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3889.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3889.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3889.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3889.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3889.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3889.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3889.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3889.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3889.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3889.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4378.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4378.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4378.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4378.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4378.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4378.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4378.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4378.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4378.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4378.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4378.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4378.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4378.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4378.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4378.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4378.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4378.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4378.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4378.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4378.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4378.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4378.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4378.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4378.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4378.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4378.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4378.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4378.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4378.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4378.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4378.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4378.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4378.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4426.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4426.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4426.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4426.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4426.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4426.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4426.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4426.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4426.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4426.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4426.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4426.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4426.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4426.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4426.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4426.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4426.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4426.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4426.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4426.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4426.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4426.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4426.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4426.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4426.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4426.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4426.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4426.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4426.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4426.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4426.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4426.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4426.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4977.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4977.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4977.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4977.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4977.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4977.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4977.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4977.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4977.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4977.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4977.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4977.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4977.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4977.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4977.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4977.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4977.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4977.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4977.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4977.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4977.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4977.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4977.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4977.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4977.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4977.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4977.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4977.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4977.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4977.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4977.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4977.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4977.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5226.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5226.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5226.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5226.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5226.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5226.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5226.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5226.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5226.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5226.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5226.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5226.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5226.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5226.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5226.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5226.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5226.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5226.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5226.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5226.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5226.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5226.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5226.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5226.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5226.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5226.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5226.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5226.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5226.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5226.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5226.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5226.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5226.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5524.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5524.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5524.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5524.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5524.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5524.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5524.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5524.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5524.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5524.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5524.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5524.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5524.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5524.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5524.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5524.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5524.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5524.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5524.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5524.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5524.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5524.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5524.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5524.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5524.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5524.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5524.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5524.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5524.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5524.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5524.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5524.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5524.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5707.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5707.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5707.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5707.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5707.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5707.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5707.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5707.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5707.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5707.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5707.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5707.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5707.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5707.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5707.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5707.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5707.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5707.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5707.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5707.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5707.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5707.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5707.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5707.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5707.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5707.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5707.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5707.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5707.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5707.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5707.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5707.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5707.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5931.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5931.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5931.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5931.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5931.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5931.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5931.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5931.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5931.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5931.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5931.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5931.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5931.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5931.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5931.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5931.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5931.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5931.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5931.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5931.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5931.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5931.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5931.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5931.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5931.xdly.x1i120 4.17 0.00 12.50 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5931.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5931.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5931.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5931.xdly.x1i175 8.33 0.00 25.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5931.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5931.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5931.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5931.xdly.xfc.x3 45.83 50.00 37.50 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5992.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5992.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5992.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5992.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5992.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5992.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5992.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5992.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5992.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5992.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5992.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5992.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5992.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5992.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5992.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5992.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5992.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5992.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5992.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5992.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5992.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5992.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5992.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5992.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5992.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5992.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5992.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5992.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5992.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5992.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5992.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5992.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5992.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6070.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6070.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6070.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6070.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6070.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6070.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6070.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6070.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6070.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6070.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6070.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6070.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6070.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6070.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6070.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6070.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6070.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6070.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6070.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6070.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6070.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6070.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6070.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6070.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6070.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6070.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6070.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6070.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6070.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6070.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6070.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6070.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6070.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6198.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6198.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6198.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6198.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6198.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6198.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6198.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6198.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6198.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6198.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6198.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6198.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6198.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6198.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6198.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6198.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6198.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6198.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6198.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6198.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6198.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6198.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6198.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6198.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6198.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6198.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6198.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6198.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6198.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6198.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6198.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6198.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6198.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6411.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6411.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6411.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6411.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6411.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6411.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6411.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6411.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6411.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6411.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6411.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6411.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6411.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6411.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6411.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6411.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6411.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6411.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6411.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6411.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6411.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6411.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6411.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6411.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6411.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6411.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6411.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6411.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6411.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6411.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6411.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6411.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6411.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6742.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6742.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6742.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6742.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6742.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6742.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6742.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6742.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6742.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6742.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6742.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6742.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6742.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6742.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6742.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6742.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6742.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6742.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6742.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6742.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6742.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6742.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6742.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6742.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6742.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6742.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6742.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6742.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6742.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6742.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6742.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6742.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6742.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7211.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7211.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7211.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7211.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7211.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7211.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7211.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7211.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7211.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7211.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7211.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7211.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7211.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7211.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7211.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7211.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7211.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7211.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7211.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7211.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7211.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7211.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7211.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7211.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7211.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7211.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7211.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7211.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7211.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7211.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7211.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7211.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7211.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7238.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7238.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7238.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7238.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7238.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7238.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7238.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7238.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7238.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7238.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7238.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7238.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7238.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7238.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7238.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7238.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7238.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7238.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7238.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7238.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7238.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7238.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7238.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7238.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7238.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7238.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7238.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7238.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7238.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7238.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7238.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7238.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7238.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7340.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7340.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7340.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7340.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7340.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7340.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7340.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7340.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7340.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7340.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7340.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7340.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7340.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7340.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7340.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7340.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7340.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7340.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7340.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7340.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7340.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7340.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7340.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7340.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7340.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7340.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7340.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7340.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7340.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7340.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7340.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7340.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7340.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7653.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7653.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7653.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7653.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7653.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7653.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7653.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7653.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7653.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7653.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7653.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7653.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7653.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7653.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7653.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7653.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7653.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7653.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7653.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7653.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7653.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7653.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7653.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7653.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7653.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7653.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7653.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7653.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7653.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7653.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7653.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7653.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7653.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7801.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7801.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7801.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7801.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7801.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7801.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7801.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7801.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7801.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7801.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7801.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7801.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7801.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7801.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7801.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7801.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7801.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7801.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7801.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7801.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7801.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7801.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7801.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7801.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7801.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7801.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7801.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7801.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7801.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7801.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7801.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7801.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7801.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7986.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7986.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7986.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7986.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7986.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7986.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7986.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7986.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7986.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7986.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7986.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7986.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7986.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7986.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7986.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7986.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7986.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7986.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7986.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7986.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7986.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7986.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7986.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7986.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7986.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7986.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7986.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7986.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7986.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7986.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7986.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7986.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7986.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8251.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8251.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8251.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8251.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8251.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8251.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8251.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8251.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8251.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8251.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8251.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8251.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8251.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8251.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8251.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8251.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8251.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8251.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8251.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8251.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8251.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8251.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8251.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8251.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8251.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8251.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8251.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8251.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8251.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8251.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8251.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8251.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8251.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9148.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9148.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9148.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9148.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9148.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9148.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9148.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9148.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9148.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9148.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9148.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9148.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9148.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9148.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9148.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9148.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9148.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9148.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9148.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9148.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9148.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9148.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9148.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9148.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9148.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9148.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9148.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9148.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9148.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9148.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9148.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9148.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9148.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9164.xdly.x1i27 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9164.xdly.x1i28 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9164.xdly.x1i29 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9164.xdly.x1i30 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9164.xdly.x1i31 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9164.xdly.x1i36 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9164.xdly.x1i40 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9164.xdly.x1i45 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9164.xdly.x1i49 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9164.xdly.x1i50 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9164.xdly.x1i51 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9164.xdly.x1i80 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9164.xdly.x1i81 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9164.xdly.x1i82 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9164.xdly.x1i83 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9164.xdly.x1i84 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9164.xdly.x1i85 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9164.xdly.x1i89 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9164.xdly.x1i93 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9164.xdly.x1i96 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9164.xdly.x1i103 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9164.xdly.x1i108 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9164.xdly.x1i112 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9164.xdly.x1i117 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9164.xdly.x1i120 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9164.xdly.x1i121 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9164.xdly.x1i122 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9164.xdly.x1i123 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9164.xdly.x1i175 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9164.xdly.x1i177 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9164.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9164.xdly.x1i193 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9164.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9178.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9178.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9178.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9178.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9178.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9178.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9178.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9178.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9178.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9178.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9178.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9178.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9178.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9178.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9178.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9178.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9178.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9178.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9178.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9178.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9178.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9178.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9178.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9178.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9178.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9178.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9178.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9178.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9178.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9178.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9178.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9178.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9178.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9403.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9403.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9403.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9403.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9403.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9403.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9403.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9403.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9403.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9403.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9403.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9403.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9403.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9403.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9403.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9403.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9403.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9403.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9403.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9403.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9403.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9403.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9403.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9403.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9403.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9403.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9403.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9403.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9403.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9403.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9403.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9403.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9403.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9425.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9425.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9425.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9425.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9425.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9425.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9425.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9425.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9425.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9425.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9425.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9425.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9425.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9425.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9425.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9425.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9425.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9425.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9425.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9425.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9425.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9425.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9425.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9425.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9425.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9425.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9425.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9425.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9425.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9425.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9425.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9425.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9425.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9788.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9788.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9788.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9788.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9788.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9788.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9788.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9788.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9788.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9788.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9788.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9788.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9788.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9788.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9788.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9788.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9788.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9788.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9788.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9788.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9788.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9788.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9788.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9788.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9788.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9788.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9788.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9788.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9788.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9788.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9788.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9788.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9788.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9915.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9915.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9915.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9915.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9915.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9915.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9915.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9915.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9915.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9915.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9915.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9915.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9915.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9915.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9915.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9915.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9915.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9915.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9915.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9915.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9915.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9915.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9915.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9915.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9915.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9915.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9915.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9915.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9915.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9915.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9915.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9915.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9915.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10217.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10217.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10217.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10217.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10217.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10217.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10217.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10217.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10217.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10217.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10217.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10217.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10217.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10217.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10217.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10217.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10217.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10217.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10217.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10217.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10217.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10217.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10217.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10217.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10217.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10217.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10217.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10217.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10217.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10217.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10217.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10217.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10217.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11361.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11361.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11361.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11361.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11361.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11361.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11361.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11361.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11361.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11361.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11361.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11361.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11361.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11361.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11361.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11361.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11361.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11361.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11361.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11361.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11361.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11361.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11361.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11361.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11361.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11361.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11361.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11361.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11361.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11361.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11361.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11361.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11361.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11605.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11605.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11605.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11605.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11605.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11605.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11605.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11605.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11605.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11605.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11605.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11605.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11605.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11605.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11605.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11605.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11605.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11605.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11605.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11605.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11605.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11605.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11605.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11605.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11605.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11605.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11605.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11605.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11605.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11605.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11605.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11605.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11605.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11664.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11664.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11664.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11664.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11664.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11664.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11664.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11664.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11664.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11664.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11664.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11664.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11664.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11664.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11664.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11664.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11664.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11664.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11664.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11664.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11664.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11664.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11664.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11664.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11664.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11664.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11664.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11664.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11664.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11664.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11664.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11664.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11664.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11943.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11943.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11943.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11943.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11943.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11943.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11943.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11943.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11943.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11943.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11943.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11943.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11943.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11943.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11943.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11943.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11943.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11943.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11943.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11943.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11943.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11943.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11943.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11943.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11943.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11943.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11943.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11943.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11943.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11943.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11943.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11943.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11943.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst100.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst100.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst100.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst100.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst100.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst100.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst100.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst100.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst100.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst100.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst100.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst100.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst100.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst100.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst100.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst100.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst100.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst100.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst100.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst100.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst100.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst100.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst100.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst100.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst100.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst100.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst100.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst100.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst100.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst100.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst100.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst100.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst100.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst89.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst89.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst89.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst89.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst89.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst89.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst89.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst89.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst89.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst89.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst89.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst89.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst89.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst89.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst89.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst89.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst89.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst89.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst89.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst89.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst89.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst89.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst89.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst89.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst89.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst89.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst89.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst89.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst89.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst89.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst89.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst89.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst89.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst254.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst254.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst254.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst254.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst254.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst254.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst254.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst254.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst254.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst254.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst254.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst254.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst254.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst254.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst254.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst254.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst254.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst254.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst254.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst254.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst254.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst254.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst254.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst254.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst254.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst254.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst254.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst254.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst254.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst254.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst254.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst254.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst254.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst382.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst382.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst382.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst382.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst382.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst382.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst382.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst382.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst382.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst382.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst382.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst382.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst382.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst382.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst382.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst382.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst382.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst382.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst382.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst382.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst382.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst382.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst382.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst382.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst382.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst382.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst382.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst382.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst382.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst382.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst382.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst382.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst382.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst401.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst401.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst401.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst401.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst401.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst401.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst401.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst401.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst401.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst401.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst401.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst401.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst401.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst401.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst401.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst401.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst401.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst401.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst401.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst401.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst401.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst401.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst401.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst401.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst401.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst401.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst401.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst401.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst401.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst401.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst401.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst401.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst401.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1046.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1046.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1046.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1046.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1046.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1046.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1046.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1046.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1046.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1046.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1046.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1046.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1046.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1046.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1046.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1046.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1046.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1046.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1046.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1046.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1046.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1046.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1046.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1046.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1046.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1046.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1046.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1046.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1046.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1046.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1046.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1046.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1046.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1394.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1394.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1394.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1394.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1394.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1394.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1394.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1394.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1394.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1394.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1394.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1394.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1394.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1394.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1394.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1394.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1394.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1394.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1394.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1394.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1394.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1394.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1394.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1394.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1394.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1394.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1394.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1394.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1394.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1394.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1394.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1394.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1394.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1629.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1629.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1629.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1629.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1629.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1629.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1629.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1629.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1629.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1629.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1629.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1629.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1629.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1629.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1629.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1629.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1629.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1629.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1629.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1629.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1629.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1629.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1629.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1629.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1629.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1629.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1629.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1629.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1629.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1629.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1629.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1629.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1629.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1862.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1862.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1862.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1862.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1862.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1862.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1862.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1862.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1862.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1862.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1862.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1862.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1862.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1862.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1862.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1862.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1862.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1862.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1862.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1862.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1862.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1862.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1862.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1862.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1862.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1862.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1862.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1862.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1862.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1862.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1862.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1862.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1862.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2210.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2210.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2210.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2210.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2210.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2210.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2210.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2210.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2210.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2210.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2210.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2210.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2210.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2210.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2210.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2210.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2210.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2210.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2210.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2210.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2210.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2210.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2210.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2210.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2210.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2210.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2210.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2210.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2210.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2210.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2210.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2210.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2210.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2250.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2250.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2250.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2250.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2250.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2250.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2250.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2250.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2250.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2250.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2250.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2250.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2250.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2250.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2250.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2250.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2250.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2250.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2250.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2250.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2250.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2250.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2250.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2250.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2250.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2250.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2250.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2250.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2250.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2250.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2250.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2250.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2250.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2461.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2461.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2461.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2461.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2461.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2461.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2461.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2461.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2461.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2461.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2461.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2461.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2461.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2461.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2461.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2461.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2461.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2461.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2461.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2461.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2461.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2461.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2461.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2461.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2461.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2461.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2461.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2461.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2461.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2461.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2461.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2461.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2461.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2711.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2711.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2711.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2711.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2711.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2711.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2711.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2711.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2711.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2711.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2711.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2711.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2711.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2711.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2711.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2711.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2711.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2711.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2711.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2711.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2711.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2711.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2711.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2711.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2711.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2711.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2711.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2711.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2711.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2711.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2711.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2711.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2711.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2731.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2731.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2731.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2731.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2731.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2731.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2731.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2731.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2731.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2731.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2731.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2731.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2731.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2731.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2731.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2731.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2731.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2731.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2731.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2731.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2731.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2731.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2731.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2731.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2731.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2731.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2731.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2731.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2731.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2731.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2731.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2731.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2731.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3889.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3889.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3889.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3889.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3889.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3889.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3889.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3889.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3889.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3889.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3889.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3889.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3889.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3889.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3889.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3889.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3889.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3889.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3889.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3889.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3889.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3889.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3889.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3889.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3889.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3889.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3889.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3889.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3889.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3889.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3889.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3889.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3889.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4378.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4378.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4378.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4378.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4378.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4378.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4378.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4378.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4378.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4378.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4378.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4378.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4378.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4378.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4378.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4378.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4378.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4378.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4378.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4378.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4378.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4378.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4378.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4378.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4378.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4378.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4378.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4378.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4378.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4378.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4378.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4378.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4378.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4426.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4426.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4426.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4426.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4426.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4426.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4426.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4426.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4426.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4426.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4426.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4426.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4426.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4426.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4426.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4426.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4426.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4426.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4426.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4426.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4426.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4426.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4426.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4426.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4426.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4426.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4426.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4426.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4426.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4426.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4426.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4426.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4426.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4977.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4977.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4977.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4977.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4977.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4977.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4977.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4977.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4977.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4977.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4977.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4977.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4977.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4977.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4977.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4977.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4977.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4977.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4977.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4977.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4977.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4977.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4977.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4977.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4977.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4977.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4977.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4977.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4977.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4977.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4977.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4977.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4977.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5226.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5226.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5226.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5226.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5226.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5226.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5226.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5226.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5226.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5226.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5226.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5226.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5226.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5226.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5226.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5226.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5226.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5226.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5226.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5226.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5226.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5226.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5226.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5226.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5226.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5226.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5226.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5226.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5226.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5226.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5226.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5226.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5226.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5524.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5524.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5524.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5524.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5524.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5524.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5524.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5524.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5524.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5524.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5524.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5524.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5524.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5524.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5524.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5524.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5524.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5524.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5524.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5524.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5524.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5524.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5524.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5524.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5524.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5524.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5524.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5524.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5524.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5524.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5524.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5524.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5524.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5707.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5707.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5707.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5707.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5707.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5707.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5707.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5707.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5707.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5707.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5707.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5707.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5707.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5707.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5707.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5707.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5707.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5707.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5707.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5707.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5707.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5707.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5707.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5707.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5707.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5707.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5707.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5707.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5707.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5707.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5707.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5707.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5707.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5931.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5931.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5931.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5931.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5931.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5931.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5931.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5931.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5931.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5931.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5931.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5931.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5931.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5931.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5931.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5931.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5931.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5931.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5931.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5931.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5931.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5931.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5931.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5931.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5931.xdly.x1i120 4.17 0.00 12.50 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5931.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5931.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5931.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5931.xdly.x1i175 8.33 0.00 25.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5931.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5931.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5931.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5931.xdly.xfc.x3 45.83 50.00 37.50 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5992.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5992.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5992.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5992.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5992.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5992.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5992.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5992.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5992.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5992.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5992.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5992.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5992.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5992.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5992.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5992.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5992.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5992.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5992.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5992.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5992.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5992.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5992.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5992.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5992.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5992.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5992.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5992.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5992.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5992.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5992.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5992.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5992.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6070.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6070.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6070.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6070.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6070.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6070.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6070.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6070.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6070.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6070.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6070.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6070.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6070.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6070.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6070.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6070.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6070.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6070.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6070.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6070.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6070.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6070.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6070.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6070.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6070.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6070.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6070.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6070.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6070.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6070.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6070.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6070.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6070.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6198.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6198.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6198.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6198.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6198.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6198.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6198.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6198.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6198.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6198.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6198.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6198.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6198.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6198.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6198.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6198.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6198.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6198.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6198.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6198.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6198.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6198.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6198.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6198.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6198.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6198.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6198.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6198.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6198.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6198.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6198.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6198.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6198.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6411.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6411.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6411.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6411.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6411.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6411.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6411.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6411.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6411.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6411.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6411.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6411.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6411.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6411.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6411.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6411.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6411.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6411.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6411.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6411.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6411.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6411.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6411.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6411.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6411.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6411.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6411.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6411.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6411.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6411.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6411.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6411.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6411.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6742.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6742.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6742.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6742.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6742.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6742.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6742.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6742.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6742.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6742.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6742.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6742.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6742.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6742.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6742.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6742.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6742.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6742.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6742.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6742.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6742.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6742.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6742.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6742.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6742.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6742.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6742.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6742.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6742.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6742.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6742.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6742.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6742.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7211.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7211.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7211.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7211.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7211.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7211.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7211.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7211.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7211.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7211.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7211.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7211.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7211.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7211.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7211.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7211.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7211.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7211.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7211.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7211.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7211.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7211.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7211.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7211.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7211.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7211.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7211.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7211.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7211.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7211.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7211.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7211.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7211.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7238.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7238.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7238.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7238.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7238.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7238.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7238.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7238.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7238.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7238.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7238.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7238.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7238.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7238.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7238.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7238.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7238.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7238.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7238.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7238.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7238.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7238.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7238.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7238.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7238.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7238.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7238.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7238.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7238.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7238.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7238.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7238.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7238.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7340.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7340.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7340.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7340.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7340.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7340.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7340.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7340.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7340.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7340.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7340.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7340.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7340.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7340.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7340.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7340.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7340.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7340.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7340.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7340.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7340.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7340.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7340.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7340.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7340.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7340.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7340.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7340.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7340.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7340.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7340.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7340.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7340.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7653.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7653.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7653.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7653.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7653.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7653.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7653.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7653.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7653.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7653.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7653.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7653.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7653.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7653.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7653.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7653.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7653.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7653.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7653.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7653.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7653.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7653.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7653.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7653.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7653.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7653.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7653.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7653.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7653.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7653.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7653.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7653.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7653.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7801.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7801.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7801.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7801.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7801.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7801.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7801.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7801.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7801.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7801.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7801.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7801.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7801.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7801.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7801.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7801.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7801.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7801.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7801.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7801.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7801.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7801.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7801.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7801.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7801.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7801.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7801.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7801.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7801.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7801.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7801.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7801.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7801.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7986.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7986.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7986.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7986.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7986.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7986.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7986.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7986.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7986.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7986.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7986.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7986.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7986.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7986.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7986.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7986.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7986.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7986.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7986.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7986.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7986.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7986.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7986.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7986.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7986.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7986.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7986.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7986.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7986.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7986.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7986.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7986.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7986.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8251.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8251.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8251.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8251.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8251.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8251.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8251.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8251.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8251.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8251.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8251.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8251.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8251.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8251.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8251.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8251.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8251.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8251.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8251.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8251.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8251.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8251.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8251.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8251.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8251.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8251.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8251.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8251.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8251.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8251.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8251.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8251.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8251.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9148.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9148.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9148.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9148.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9148.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9148.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9148.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9148.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9148.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9148.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9148.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9148.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9148.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9148.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9148.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9148.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9148.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9148.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9148.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9148.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9148.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9148.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9148.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9148.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9148.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9148.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9148.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9148.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9148.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9148.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9148.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9148.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9148.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9164.xdly.x1i27 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9164.xdly.x1i28 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9164.xdly.x1i29 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9164.xdly.x1i30 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9164.xdly.x1i31 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9164.xdly.x1i36 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9164.xdly.x1i40 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9164.xdly.x1i45 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9164.xdly.x1i49 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9164.xdly.x1i50 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9164.xdly.x1i51 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9164.xdly.x1i80 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9164.xdly.x1i81 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9164.xdly.x1i82 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9164.xdly.x1i83 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9164.xdly.x1i84 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9164.xdly.x1i85 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9164.xdly.x1i89 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9164.xdly.x1i93 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9164.xdly.x1i96 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9164.xdly.x1i103 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9164.xdly.x1i108 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9164.xdly.x1i112 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9164.xdly.x1i117 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9164.xdly.x1i120 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9164.xdly.x1i121 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9164.xdly.x1i122 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9164.xdly.x1i123 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9164.xdly.x1i175 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9164.xdly.x1i177 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9164.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9164.xdly.x1i193 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9164.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9178.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9178.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9178.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9178.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9178.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9178.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9178.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9178.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9178.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9178.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9178.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9178.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9178.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9178.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9178.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9178.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9178.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9178.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9178.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9178.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9178.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9178.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9178.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9178.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9178.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9178.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9178.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9178.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9178.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9178.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9178.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9178.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9178.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9403.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9403.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9403.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9403.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9403.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9403.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9403.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9403.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9403.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9403.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9403.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9403.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9403.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9403.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9403.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9403.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9403.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9403.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9403.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9403.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9403.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9403.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9403.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9403.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9403.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9403.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9403.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9403.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9403.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9403.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9403.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9403.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9403.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9425.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9425.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9425.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9425.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9425.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9425.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9425.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9425.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9425.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9425.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9425.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9425.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9425.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9425.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9425.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9425.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9425.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9425.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9425.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9425.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9425.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9425.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9425.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9425.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9425.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9425.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9425.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9425.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9425.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9425.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9425.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9425.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9425.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9788.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9788.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9788.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9788.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9788.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9788.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9788.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9788.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9788.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9788.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9788.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9788.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9788.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9788.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9788.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9788.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9788.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9788.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9788.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9788.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9788.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9788.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9788.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9788.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9788.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9788.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9788.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9788.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9788.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9788.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9788.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9788.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9788.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9915.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9915.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9915.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9915.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9915.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9915.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9915.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9915.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9915.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9915.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9915.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9915.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9915.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9915.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9915.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9915.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9915.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9915.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9915.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9915.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9915.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9915.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9915.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9915.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9915.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9915.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9915.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9915.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9915.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9915.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9915.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9915.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9915.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10217.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10217.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10217.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10217.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10217.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10217.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10217.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10217.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10217.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10217.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10217.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10217.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10217.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10217.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10217.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10217.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10217.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10217.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10217.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10217.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10217.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10217.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10217.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10217.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10217.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10217.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10217.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10217.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10217.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10217.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10217.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10217.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10217.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11361.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11361.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11361.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11361.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11361.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11361.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11361.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11361.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11361.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11361.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11361.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11361.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11361.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11361.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11361.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11361.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11361.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11361.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11361.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11361.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11361.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11361.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11361.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11361.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11361.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11361.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11361.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11361.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11361.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11361.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11361.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11361.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11361.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11605.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11605.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11605.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11605.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11605.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11605.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11605.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11605.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11605.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11605.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11605.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11605.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11605.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11605.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11605.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11605.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11605.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11605.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11605.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11605.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11605.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11605.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11605.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11605.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11605.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11605.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11605.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11605.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11605.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11605.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11605.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11605.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11605.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11664.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11664.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11664.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11664.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11664.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11664.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11664.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11664.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11664.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11664.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11664.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11664.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11664.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11664.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11664.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11664.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11664.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11664.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11664.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11664.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11664.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11664.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11664.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11664.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11664.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11664.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11664.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11664.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11664.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11664.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11664.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11664.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11664.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11943.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11943.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11943.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11943.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11943.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11943.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11943.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11943.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11943.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11943.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11943.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11943.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11943.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11943.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11943.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11943.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11943.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11943.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11943.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11943.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11943.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11943.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11943.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11943.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11943.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11943.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11943.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11943.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11943.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11943.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11943.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11943.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11943.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst100.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst100.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst100.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst100.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst100.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst100.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst100.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst100.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst100.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst100.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst100.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst100.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst100.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst100.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst100.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst100.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst100.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst100.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst100.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst100.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst100.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst100.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst100.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst100.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst100.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst100.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst100.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst100.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst100.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst100.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst100.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst100.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst100.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst89.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst89.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst89.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst89.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst89.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst89.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst89.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst89.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst89.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst89.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst89.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst89.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst89.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst89.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst89.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst89.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst89.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst89.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst89.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst89.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst89.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst89.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst89.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst89.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst89.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst89.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst89.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst89.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst89.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst89.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst89.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst89.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst89.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst254.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst254.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst254.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst254.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst254.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst254.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst254.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst254.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst254.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst254.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst254.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst254.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst254.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst254.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst254.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst254.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst254.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst254.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst254.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst254.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst254.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst254.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst254.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst254.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst254.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst254.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst254.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst254.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst254.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst254.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst254.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst254.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst254.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst382.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst382.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst382.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst382.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst382.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst382.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst382.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst382.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst382.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst382.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst382.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst382.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst382.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst382.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst382.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst382.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst382.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst382.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst382.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst382.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst382.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst382.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst382.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst382.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst382.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst382.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst382.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst382.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst382.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst382.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst382.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst382.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst382.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst401.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst401.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst401.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst401.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst401.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst401.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst401.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst401.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst401.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst401.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst401.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst401.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst401.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst401.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst401.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst401.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst401.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst401.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst401.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst401.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst401.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst401.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst401.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst401.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst401.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst401.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst401.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst401.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst401.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst401.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst401.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst401.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst401.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1046.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1046.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1046.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1046.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1046.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1046.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1046.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1046.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1046.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1046.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1046.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1046.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1046.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1046.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1046.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1046.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1046.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1046.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1046.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1046.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1046.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1046.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1046.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1046.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1046.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1046.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1046.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1046.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1046.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1046.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1046.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1046.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1046.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1394.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1394.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1394.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1394.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1394.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1394.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1394.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1394.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1394.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1394.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1394.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1394.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1394.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1394.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1394.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1394.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1394.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1394.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1394.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1394.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1394.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1394.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1394.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1394.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1394.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1394.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1394.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1394.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1394.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1394.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1394.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1394.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1394.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1629.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1629.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1629.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1629.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1629.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1629.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1629.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1629.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1629.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1629.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1629.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1629.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1629.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1629.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1629.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1629.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1629.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1629.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1629.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1629.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1629.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1629.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1629.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1629.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1629.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1629.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1629.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1629.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1629.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1629.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1629.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1629.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1629.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1862.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1862.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1862.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1862.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1862.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1862.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1862.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1862.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1862.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1862.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1862.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1862.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1862.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1862.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1862.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1862.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1862.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1862.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1862.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1862.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1862.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1862.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1862.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1862.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1862.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1862.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1862.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1862.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1862.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1862.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1862.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1862.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1862.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2210.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2210.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2210.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2210.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2210.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2210.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2210.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2210.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2210.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2210.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2210.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2210.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2210.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2210.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2210.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2210.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2210.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2210.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2210.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2210.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2210.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2210.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2210.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2210.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2210.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2210.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2210.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2210.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2210.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2210.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2210.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2210.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2210.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2250.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2250.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2250.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2250.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2250.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2250.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2250.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2250.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2250.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2250.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2250.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2250.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2250.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2250.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2250.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2250.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2250.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2250.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2250.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2250.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2250.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2250.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2250.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2250.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2250.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2250.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2250.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2250.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2250.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2250.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2250.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2250.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2250.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2461.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2461.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2461.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2461.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2461.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2461.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2461.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2461.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2461.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2461.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2461.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2461.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2461.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2461.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2461.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2461.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2461.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2461.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2461.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2461.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2461.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2461.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2461.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2461.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2461.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2461.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2461.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2461.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2461.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2461.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2461.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2461.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2461.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2711.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2711.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2711.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2711.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2711.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2711.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2711.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2711.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2711.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2711.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2711.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2711.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2711.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2711.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2711.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2711.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2711.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2711.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2711.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2711.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2711.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2711.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2711.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2711.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2711.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2711.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2711.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2711.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2711.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2711.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2711.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2711.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2711.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2731.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2731.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2731.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2731.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2731.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2731.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2731.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2731.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2731.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2731.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2731.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2731.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2731.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2731.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2731.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2731.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2731.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2731.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2731.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2731.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2731.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2731.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2731.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2731.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2731.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2731.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2731.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2731.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2731.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2731.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2731.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2731.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2731.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3889.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3889.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3889.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3889.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3889.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3889.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3889.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3889.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3889.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3889.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3889.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3889.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3889.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3889.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3889.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3889.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3889.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3889.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3889.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3889.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3889.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3889.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3889.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3889.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3889.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3889.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3889.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3889.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3889.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3889.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3889.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3889.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3889.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4378.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4378.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4378.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4378.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4378.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4378.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4378.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4378.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4378.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4378.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4378.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4378.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4378.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4378.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4378.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4378.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4378.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4378.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4378.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4378.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4378.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4378.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4378.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4378.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4378.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4378.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4378.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4378.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4378.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4378.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4378.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4378.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4378.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4426.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4426.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4426.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4426.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4426.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4426.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4426.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4426.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4426.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4426.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4426.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4426.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4426.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4426.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4426.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4426.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4426.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4426.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4426.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4426.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4426.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4426.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4426.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4426.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4426.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4426.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4426.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4426.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4426.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4426.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4426.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4426.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4426.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4977.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4977.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4977.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4977.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4977.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4977.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4977.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4977.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4977.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4977.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4977.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4977.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4977.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4977.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4977.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4977.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4977.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4977.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4977.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4977.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4977.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4977.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4977.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4977.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4977.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4977.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4977.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4977.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4977.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4977.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4977.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4977.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4977.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5226.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5226.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5226.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5226.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5226.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5226.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5226.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5226.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5226.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5226.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5226.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5226.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5226.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5226.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5226.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5226.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5226.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5226.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5226.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5226.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5226.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5226.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5226.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5226.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5226.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5226.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5226.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5226.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5226.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5226.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5226.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5226.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5226.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5524.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5524.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5524.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5524.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5524.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5524.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5524.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5524.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5524.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5524.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5524.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5524.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5524.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5524.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5524.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5524.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5524.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5524.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5524.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5524.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5524.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5524.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5524.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5524.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5524.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5524.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5524.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5524.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5524.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5524.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5524.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5524.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5524.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5707.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5707.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5707.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5707.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5707.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5707.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5707.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5707.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5707.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5707.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5707.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5707.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5707.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5707.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5707.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5707.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5707.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5707.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5707.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5707.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5707.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5707.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5707.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5707.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5707.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5707.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5707.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5707.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5707.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5707.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5707.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5707.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5707.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5931.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5931.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5931.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5931.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5931.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5931.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5931.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5931.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5931.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5931.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5931.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5931.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5931.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5931.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5931.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5931.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5931.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5931.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5931.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5931.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5931.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5931.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5931.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5931.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5931.xdly.x1i120 4.17 0.00 12.50 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5931.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5931.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5931.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5931.xdly.x1i175 8.33 0.00 25.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5931.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5931.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5931.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5931.xdly.xfc.x3 45.83 50.00 37.50 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5992.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5992.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5992.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5992.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5992.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5992.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5992.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5992.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5992.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5992.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5992.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5992.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5992.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5992.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5992.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5992.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5992.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5992.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5992.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5992.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5992.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5992.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5992.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5992.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5992.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5992.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5992.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5992.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5992.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5992.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5992.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5992.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5992.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6070.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6070.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6070.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6070.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6070.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6070.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6070.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6070.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6070.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6070.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6070.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6070.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6070.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6070.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6070.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6070.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6070.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6070.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6070.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6070.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6070.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6070.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6070.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6070.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6070.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6070.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6070.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6070.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6070.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6070.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6070.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6070.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6070.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6198.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6198.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6198.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6198.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6198.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6198.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6198.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6198.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6198.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6198.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6198.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6198.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6198.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6198.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6198.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6198.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6198.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6198.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6198.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6198.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6198.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6198.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6198.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6198.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6198.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6198.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6198.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6198.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6198.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6198.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6198.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6198.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6198.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6411.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6411.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6411.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6411.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6411.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6411.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6411.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6411.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6411.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6411.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6411.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6411.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6411.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6411.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6411.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6411.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6411.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6411.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6411.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6411.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6411.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6411.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6411.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6411.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6411.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6411.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6411.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6411.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6411.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6411.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6411.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6411.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6411.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6742.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6742.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6742.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6742.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6742.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6742.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6742.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6742.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6742.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6742.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6742.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6742.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6742.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6742.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6742.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6742.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6742.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6742.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6742.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6742.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6742.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6742.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6742.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6742.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6742.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6742.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6742.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6742.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6742.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6742.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6742.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6742.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6742.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7211.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7211.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7211.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7211.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7211.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7211.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7211.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7211.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7211.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7211.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7211.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7211.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7211.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7211.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7211.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7211.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7211.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7211.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7211.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7211.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7211.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7211.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7211.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7211.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7211.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7211.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7211.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7211.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7211.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7211.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7211.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7211.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7211.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7238.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7238.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7238.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7238.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7238.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7238.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7238.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7238.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7238.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7238.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7238.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7238.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7238.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7238.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7238.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7238.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7238.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7238.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7238.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7238.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7238.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7238.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7238.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7238.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7238.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7238.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7238.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7238.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7238.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7238.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7238.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7238.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7238.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7340.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7340.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7340.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7340.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7340.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7340.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7340.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7340.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7340.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7340.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7340.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7340.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7340.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7340.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7340.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7340.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7340.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7340.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7340.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7340.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7340.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7340.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7340.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7340.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7340.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7340.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7340.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7340.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7340.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7340.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7340.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7340.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7340.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7653.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7653.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7653.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7653.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7653.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7653.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7653.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7653.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7653.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7653.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7653.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7653.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7653.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7653.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7653.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7653.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7653.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7653.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7653.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7653.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7653.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7653.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7653.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7653.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7653.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7653.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7653.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7653.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7653.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7653.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7653.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7653.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7653.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7801.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7801.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7801.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7801.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7801.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7801.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7801.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7801.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7801.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7801.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7801.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7801.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7801.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7801.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7801.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7801.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7801.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7801.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7801.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7801.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7801.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7801.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7801.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7801.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7801.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7801.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7801.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7801.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7801.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7801.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7801.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7801.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7801.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7986.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7986.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7986.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7986.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7986.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7986.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7986.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7986.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7986.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7986.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7986.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7986.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7986.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7986.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7986.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7986.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7986.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7986.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7986.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7986.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7986.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7986.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7986.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7986.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7986.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7986.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7986.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7986.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7986.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7986.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7986.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7986.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7986.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8251.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8251.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8251.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8251.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8251.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8251.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8251.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8251.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8251.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8251.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8251.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8251.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8251.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8251.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8251.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8251.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8251.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8251.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8251.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8251.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8251.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8251.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8251.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8251.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8251.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8251.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8251.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8251.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8251.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8251.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8251.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8251.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8251.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9148.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9148.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9148.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9148.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9148.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9148.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9148.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9148.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9148.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9148.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9148.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9148.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9148.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9148.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9148.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9148.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9148.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9148.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9148.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9148.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9148.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9148.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9148.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9148.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9148.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9148.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9148.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9148.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9148.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9148.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9148.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9148.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9148.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9164.xdly.x1i27 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9164.xdly.x1i28 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9164.xdly.x1i29 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9164.xdly.x1i30 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9164.xdly.x1i31 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9164.xdly.x1i36 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9164.xdly.x1i40 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9164.xdly.x1i45 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9164.xdly.x1i49 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9164.xdly.x1i50 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9164.xdly.x1i51 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9164.xdly.x1i80 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9164.xdly.x1i81 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9164.xdly.x1i82 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9164.xdly.x1i83 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9164.xdly.x1i84 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9164.xdly.x1i85 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9164.xdly.x1i89 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9164.xdly.x1i93 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9164.xdly.x1i96 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9164.xdly.x1i103 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9164.xdly.x1i108 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9164.xdly.x1i112 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9164.xdly.x1i117 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9164.xdly.x1i120 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9164.xdly.x1i121 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9164.xdly.x1i122 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9164.xdly.x1i123 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9164.xdly.x1i175 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9164.xdly.x1i177 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9164.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9164.xdly.x1i193 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9164.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9178.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9178.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9178.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9178.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9178.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9178.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9178.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9178.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9178.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9178.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9178.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9178.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9178.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9178.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9178.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9178.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9178.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9178.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9178.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9178.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9178.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9178.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9178.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9178.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9178.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9178.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9178.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9178.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9178.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9178.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9178.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9178.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9178.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9403.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9403.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9403.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9403.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9403.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9403.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9403.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9403.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9403.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9403.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9403.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9403.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9403.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9403.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9403.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9403.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9403.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9403.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9403.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9403.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9403.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9403.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9403.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9403.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9403.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9403.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9403.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9403.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9403.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9403.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9403.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9403.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9403.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9425.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9425.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9425.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9425.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9425.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9425.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9425.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9425.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9425.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9425.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9425.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9425.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9425.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9425.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9425.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9425.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9425.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9425.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9425.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9425.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9425.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9425.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9425.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9425.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9425.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9425.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9425.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9425.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9425.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9425.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9425.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9425.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9425.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9788.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9788.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9788.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9788.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9788.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9788.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9788.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9788.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9788.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9788.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9788.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9788.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9788.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9788.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9788.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9788.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9788.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9788.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9788.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9788.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9788.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9788.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9788.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9788.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9788.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9788.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9788.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9788.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9788.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9788.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9788.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9788.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9788.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9915.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9915.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9915.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9915.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9915.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9915.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9915.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9915.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9915.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9915.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9915.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9915.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9915.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9915.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9915.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9915.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9915.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9915.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9915.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9915.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9915.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9915.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9915.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9915.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9915.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9915.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9915.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9915.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9915.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9915.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9915.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9915.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9915.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10217.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10217.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10217.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10217.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10217.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10217.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10217.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10217.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10217.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10217.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10217.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10217.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10217.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10217.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10217.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10217.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10217.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10217.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10217.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10217.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10217.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10217.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10217.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10217.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10217.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10217.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10217.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10217.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10217.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10217.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10217.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10217.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10217.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11361.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11361.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11361.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11361.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11361.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11361.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11361.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11361.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11361.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11361.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11361.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11361.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11361.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11361.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11361.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11361.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11361.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11361.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11361.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11361.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11361.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11361.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11361.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11361.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11361.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11361.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11361.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11361.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11361.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11361.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11361.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11361.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11361.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11605.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11605.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11605.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11605.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11605.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11605.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11605.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11605.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11605.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11605.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11605.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11605.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11605.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11605.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11605.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11605.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11605.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11605.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11605.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11605.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11605.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11605.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11605.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11605.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11605.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11605.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11605.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11605.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11605.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11605.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11605.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11605.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11605.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11664.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11664.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11664.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11664.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11664.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11664.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11664.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11664.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11664.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11664.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11664.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11664.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11664.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11664.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11664.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11664.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11664.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11664.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11664.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11664.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11664.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11664.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11664.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11664.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11664.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11664.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11664.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11664.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11664.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11664.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11664.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11664.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11664.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11943.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11943.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11943.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11943.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11943.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11943.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11943.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11943.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11943.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11943.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11943.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11943.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11943.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11943.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11943.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11943.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11943.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11943.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11943.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11943.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11943.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11943.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11943.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11943.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11943.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11943.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11943.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11943.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11943.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11943.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11943.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11943.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11943.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst100.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst100.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst100.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst100.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst100.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst100.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst100.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst100.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst100.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst100.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst100.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst100.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst100.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst100.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst100.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst100.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst100.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst100.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst100.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst100.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst100.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst100.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst100.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst100.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst100.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst100.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst100.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst100.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst100.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst100.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst100.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst100.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst100.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst89.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst89.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst89.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst89.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst89.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst89.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst89.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst89.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst89.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst89.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst89.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst89.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst89.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst89.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst89.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst89.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst89.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst89.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst89.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst89.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst89.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst89.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst89.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst89.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst89.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst89.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst89.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst89.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst89.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst89.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst89.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst89.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst89.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst254.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst254.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst254.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst254.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst254.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst254.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst254.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst254.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst254.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst254.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst254.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst254.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst254.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst254.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst254.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst254.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst254.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst254.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst254.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst254.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst254.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst254.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst254.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst254.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst254.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst254.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst254.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst254.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst254.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst254.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst254.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst254.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst254.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst382.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst382.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst382.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst382.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst382.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst382.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst382.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst382.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst382.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst382.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst382.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst382.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst382.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst382.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst382.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst382.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst382.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst382.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst382.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst382.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst382.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst382.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst382.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst382.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst382.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst382.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst382.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst382.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst382.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst382.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst382.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst382.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst382.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst401.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst401.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst401.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst401.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst401.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst401.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst401.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst401.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst401.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst401.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst401.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst401.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst401.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst401.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst401.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst401.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst401.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst401.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst401.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst401.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst401.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst401.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst401.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst401.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst401.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst401.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst401.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst401.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst401.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst401.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst401.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst401.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst401.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1046.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1046.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1046.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1046.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1046.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1046.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1046.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1046.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1046.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1046.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1046.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1046.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1046.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1046.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1046.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1046.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1046.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1046.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1046.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1046.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1046.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1046.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1046.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1046.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1046.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1046.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1046.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1046.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1046.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1046.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1046.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1046.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1046.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1394.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1394.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1394.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1394.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1394.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1394.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1394.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1394.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1394.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1394.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1394.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1394.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1394.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1394.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1394.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1394.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1394.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1394.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1394.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1394.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1394.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1394.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1394.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1394.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1394.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1394.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1394.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1394.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1394.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1394.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1394.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1394.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1394.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1629.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1629.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1629.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1629.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1629.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1629.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1629.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1629.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1629.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1629.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1629.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1629.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1629.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1629.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1629.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1629.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1629.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1629.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1629.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1629.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1629.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1629.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1629.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1629.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1629.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1629.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1629.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1629.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1629.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1629.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1629.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1629.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1629.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1862.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1862.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1862.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1862.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1862.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1862.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1862.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1862.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1862.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1862.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1862.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1862.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1862.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1862.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1862.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1862.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1862.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1862.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1862.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1862.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1862.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1862.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1862.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1862.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1862.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1862.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1862.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1862.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1862.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1862.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1862.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1862.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1862.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2210.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2210.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2210.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2210.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2210.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2210.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2210.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2210.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2210.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2210.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2210.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2210.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2210.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2210.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2210.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2210.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2210.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2210.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2210.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2210.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2210.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2210.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2210.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2210.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2210.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2210.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2210.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2210.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2210.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2210.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2210.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2210.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2210.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2250.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2250.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2250.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2250.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2250.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2250.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2250.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2250.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2250.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2250.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2250.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2250.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2250.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2250.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2250.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2250.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2250.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2250.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2250.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2250.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2250.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2250.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2250.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2250.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2250.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2250.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2250.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2250.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2250.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2250.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2250.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2250.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2250.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2461.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2461.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2461.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2461.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2461.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2461.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2461.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2461.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2461.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2461.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2461.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2461.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2461.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2461.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2461.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2461.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2461.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2461.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2461.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2461.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2461.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2461.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2461.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2461.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2461.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2461.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2461.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2461.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2461.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2461.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2461.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2461.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2461.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2711.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2711.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2711.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2711.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2711.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2711.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2711.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2711.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2711.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2711.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2711.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2711.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2711.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2711.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2711.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2711.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2711.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2711.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2711.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2711.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2711.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2711.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2711.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2711.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2711.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2711.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2711.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2711.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2711.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2711.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2711.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2711.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2711.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2731.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2731.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2731.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2731.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2731.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2731.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2731.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2731.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2731.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2731.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2731.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2731.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2731.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2731.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2731.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2731.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2731.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2731.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2731.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2731.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2731.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2731.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2731.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2731.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2731.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2731.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2731.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2731.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2731.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2731.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2731.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2731.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2731.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3889.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3889.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3889.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3889.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3889.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3889.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3889.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3889.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3889.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3889.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3889.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3889.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3889.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3889.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3889.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3889.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3889.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3889.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3889.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3889.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3889.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3889.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3889.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3889.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3889.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3889.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3889.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3889.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3889.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3889.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3889.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3889.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3889.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4378.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4378.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4378.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4378.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4378.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4378.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4378.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4378.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4378.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4378.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4378.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4378.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4378.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4378.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4378.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4378.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4378.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4378.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4378.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4378.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4378.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4378.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4378.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4378.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4378.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4378.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4378.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4378.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4378.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4378.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4378.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4378.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4378.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4426.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4426.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4426.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4426.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4426.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4426.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4426.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4426.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4426.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4426.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4426.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4426.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4426.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4426.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4426.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4426.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4426.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4426.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4426.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4426.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4426.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4426.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4426.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4426.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4426.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4426.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4426.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4426.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4426.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4426.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4426.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4426.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4426.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4977.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4977.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4977.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4977.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4977.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4977.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4977.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4977.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4977.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4977.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4977.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4977.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4977.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4977.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4977.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4977.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4977.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4977.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4977.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4977.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4977.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4977.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4977.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4977.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4977.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4977.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4977.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4977.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4977.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4977.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4977.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4977.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4977.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5226.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5226.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5226.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5226.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5226.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5226.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5226.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5226.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5226.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5226.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5226.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5226.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5226.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5226.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5226.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5226.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5226.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5226.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5226.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5226.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5226.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5226.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5226.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5226.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5226.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5226.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5226.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5226.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5226.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5226.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5226.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5226.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5226.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5524.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5524.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5524.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5524.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5524.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5524.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5524.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5524.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5524.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5524.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5524.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5524.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5524.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5524.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5524.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5524.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5524.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5524.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5524.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5524.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5524.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5524.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5524.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5524.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5524.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5524.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5524.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5524.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5524.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5524.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5524.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5524.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5524.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5707.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5707.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5707.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5707.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5707.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5707.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5707.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5707.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5707.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5707.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5707.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5707.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5707.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5707.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5707.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5707.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5707.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5707.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5707.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5707.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5707.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5707.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5707.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5707.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5707.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5707.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5707.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5707.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5707.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5707.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5707.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5707.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5707.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5931.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5931.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5931.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5931.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5931.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5931.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5931.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5931.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5931.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5931.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5931.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5931.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5931.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5931.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5931.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5931.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5931.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5931.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5931.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5931.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5931.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5931.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5931.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5931.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5931.xdly.x1i120 4.17 0.00 12.50 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5931.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5931.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5931.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5931.xdly.x1i175 8.33 0.00 25.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5931.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5931.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5931.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5931.xdly.xfc.x3 45.83 50.00 37.50 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5992.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5992.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5992.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5992.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5992.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5992.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5992.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5992.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5992.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5992.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5992.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5992.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5992.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5992.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5992.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5992.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5992.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5992.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5992.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5992.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5992.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5992.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5992.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5992.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5992.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5992.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5992.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5992.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5992.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5992.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5992.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5992.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5992.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6070.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6070.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6070.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6070.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6070.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6070.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6070.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6070.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6070.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6070.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6070.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6070.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6070.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6070.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6070.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6070.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6070.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6070.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6070.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6070.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6070.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6070.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6070.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6070.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6070.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6070.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6070.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6070.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6070.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6070.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6070.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6070.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6070.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6198.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6198.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6198.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6198.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6198.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6198.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6198.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6198.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6198.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6198.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6198.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6198.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6198.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6198.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6198.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6198.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6198.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6198.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6198.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6198.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6198.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6198.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6198.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6198.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6198.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6198.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6198.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6198.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6198.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6198.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6198.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6198.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6198.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6411.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6411.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6411.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6411.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6411.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6411.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6411.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6411.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6411.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6411.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6411.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6411.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6411.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6411.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6411.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6411.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6411.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6411.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6411.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6411.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6411.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6411.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6411.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6411.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6411.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6411.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6411.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6411.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6411.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6411.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6411.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6411.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6411.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6742.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6742.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6742.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6742.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6742.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6742.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6742.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6742.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6742.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6742.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6742.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6742.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6742.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6742.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6742.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6742.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6742.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6742.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6742.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6742.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6742.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6742.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6742.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6742.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6742.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6742.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6742.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6742.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6742.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6742.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6742.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6742.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6742.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7211.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7211.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7211.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7211.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7211.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7211.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7211.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7211.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7211.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7211.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7211.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7211.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7211.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7211.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7211.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7211.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7211.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7211.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7211.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7211.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7211.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7211.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7211.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7211.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7211.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7211.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7211.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7211.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7211.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7211.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7211.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7211.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7211.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7238.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7238.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7238.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7238.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7238.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7238.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7238.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7238.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7238.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7238.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7238.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7238.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7238.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7238.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7238.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7238.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7238.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7238.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7238.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7238.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7238.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7238.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7238.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7238.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7238.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7238.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7238.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7238.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7238.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7238.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7238.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7238.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7238.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7340.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7340.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7340.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7340.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7340.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7340.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7340.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7340.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7340.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7340.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7340.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7340.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7340.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7340.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7340.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7340.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7340.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7340.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7340.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7340.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7340.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7340.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7340.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7340.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7340.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7340.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7340.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7340.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7340.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7340.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7340.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7340.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7340.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7653.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7653.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7653.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7653.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7653.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7653.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7653.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7653.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7653.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7653.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7653.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7653.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7653.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7653.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7653.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7653.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7653.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7653.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7653.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7653.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7653.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7653.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7653.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7653.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7653.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7653.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7653.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7653.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7653.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7653.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7653.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7653.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7653.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7801.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7801.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7801.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7801.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7801.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7801.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7801.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7801.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7801.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7801.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7801.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7801.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7801.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7801.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7801.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7801.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7801.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7801.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7801.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7801.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7801.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7801.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7801.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7801.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7801.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7801.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7801.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7801.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7801.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7801.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7801.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7801.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7801.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7986.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7986.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7986.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7986.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7986.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7986.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7986.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7986.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7986.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7986.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7986.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7986.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7986.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7986.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7986.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7986.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7986.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7986.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7986.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7986.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7986.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7986.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7986.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7986.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7986.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7986.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7986.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7986.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7986.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7986.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7986.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7986.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7986.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8251.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8251.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8251.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8251.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8251.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8251.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8251.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8251.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8251.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8251.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8251.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8251.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8251.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8251.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8251.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8251.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8251.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8251.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8251.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8251.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8251.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8251.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8251.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8251.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8251.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8251.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8251.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8251.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8251.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8251.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8251.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8251.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8251.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9148.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9148.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9148.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9148.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9148.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9148.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9148.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9148.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9148.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9148.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9148.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9148.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9148.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9148.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9148.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9148.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9148.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9148.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9148.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9148.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9148.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9148.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9148.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9148.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9148.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9148.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9148.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9148.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9148.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9148.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9148.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9148.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9148.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9164.xdly.x1i27 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9164.xdly.x1i28 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9164.xdly.x1i29 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9164.xdly.x1i30 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9164.xdly.x1i31 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9164.xdly.x1i36 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9164.xdly.x1i40 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9164.xdly.x1i45 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9164.xdly.x1i49 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9164.xdly.x1i50 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9164.xdly.x1i51 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9164.xdly.x1i80 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9164.xdly.x1i81 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9164.xdly.x1i82 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9164.xdly.x1i83 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9164.xdly.x1i84 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9164.xdly.x1i85 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9164.xdly.x1i89 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9164.xdly.x1i93 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9164.xdly.x1i96 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9164.xdly.x1i103 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9164.xdly.x1i108 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9164.xdly.x1i112 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9164.xdly.x1i117 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9164.xdly.x1i120 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9164.xdly.x1i121 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9164.xdly.x1i122 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9164.xdly.x1i123 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9164.xdly.x1i175 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9164.xdly.x1i177 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9164.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9164.xdly.x1i193 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9164.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9178.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9178.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9178.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9178.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9178.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9178.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9178.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9178.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9178.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9178.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9178.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9178.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9178.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9178.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9178.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9178.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9178.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9178.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9178.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9178.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9178.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9178.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9178.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9178.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9178.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9178.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9178.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9178.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9178.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9178.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9178.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9178.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9178.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9403.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9403.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9403.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9403.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9403.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9403.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9403.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9403.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9403.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9403.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9403.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9403.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9403.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9403.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9403.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9403.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9403.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9403.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9403.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9403.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9403.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9403.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9403.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9403.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9403.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9403.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9403.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9403.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9403.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9403.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9403.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9403.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9403.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9425.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9425.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9425.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9425.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9425.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9425.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9425.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9425.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9425.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9425.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9425.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9425.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9425.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9425.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9425.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9425.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9425.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9425.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9425.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9425.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9425.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9425.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9425.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9425.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9425.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9425.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9425.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9425.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9425.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9425.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9425.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9425.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9425.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9788.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9788.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9788.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9788.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9788.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9788.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9788.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9788.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9788.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9788.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9788.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9788.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9788.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9788.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9788.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9788.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9788.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9788.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9788.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9788.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9788.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9788.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9788.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9788.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9788.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9788.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9788.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9788.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9788.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9788.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9788.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9788.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9788.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9915.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9915.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9915.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9915.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9915.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9915.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9915.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9915.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9915.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9915.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9915.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9915.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9915.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9915.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9915.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9915.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9915.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9915.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9915.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9915.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9915.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9915.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9915.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9915.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9915.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9915.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9915.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9915.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9915.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9915.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9915.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9915.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9915.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10217.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10217.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10217.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10217.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10217.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10217.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10217.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10217.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10217.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10217.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10217.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10217.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10217.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10217.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10217.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10217.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10217.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10217.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10217.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10217.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10217.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10217.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10217.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10217.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10217.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10217.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10217.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10217.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10217.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10217.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10217.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10217.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10217.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11361.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11361.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11361.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11361.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11361.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11361.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11361.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11361.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11361.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11361.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11361.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11361.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11361.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11361.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11361.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11361.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11361.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11361.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11361.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11361.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11361.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11361.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11361.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11361.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11361.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11361.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11361.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11361.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11361.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11361.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11361.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11361.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11361.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11605.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11605.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11605.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11605.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11605.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11605.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11605.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11605.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11605.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11605.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11605.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11605.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11605.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11605.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11605.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11605.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11605.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11605.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11605.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11605.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11605.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11605.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11605.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11605.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11605.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11605.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11605.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11605.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11605.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11605.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11605.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11605.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11605.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11664.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11664.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11664.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11664.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11664.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11664.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11664.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11664.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11664.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11664.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11664.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11664.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11664.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11664.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11664.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11664.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11664.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11664.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11664.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11664.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11664.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11664.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11664.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11664.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11664.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11664.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11664.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11664.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11664.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11664.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11664.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11664.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11664.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11943.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11943.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11943.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11943.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11943.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11943.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11943.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11943.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11943.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11943.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11943.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11943.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11943.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11943.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11943.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11943.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11943.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11943.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11943.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11943.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11943.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11943.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11943.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11943.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11943.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11943.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11943.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11943.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11943.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11943.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11943.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11943.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11943.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst100.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst100.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst100.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst100.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst100.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst100.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst100.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst100.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst100.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst100.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst100.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst100.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst100.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst100.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst100.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst100.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst100.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst100.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst100.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst100.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst100.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst100.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst100.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst100.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst100.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst100.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst100.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst100.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst100.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst100.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst100.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst100.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst100.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst89.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst89.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst89.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst89.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst89.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst89.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst89.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst89.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst89.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst89.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst89.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst89.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst89.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst89.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst89.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst89.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst89.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst89.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst89.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst89.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst89.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst89.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst89.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst89.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst89.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst89.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst89.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst89.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst89.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst89.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst89.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst89.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst89.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst254.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst254.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst254.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst254.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst254.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst254.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst254.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst254.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst254.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst254.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst254.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst254.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst254.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst254.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst254.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst254.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst254.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst254.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst254.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst254.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst254.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst254.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst254.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst254.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst254.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst254.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst254.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst254.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst254.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst254.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst254.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst254.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst254.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst382.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst382.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst382.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst382.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst382.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst382.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst382.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst382.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst382.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst382.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst382.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst382.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst382.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst382.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst382.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst382.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst382.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst382.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst382.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst382.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst382.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst382.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst382.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst382.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst382.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst382.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst382.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst382.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst382.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst382.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst382.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst382.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst382.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst401.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst401.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst401.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst401.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst401.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst401.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst401.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst401.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst401.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst401.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst401.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst401.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst401.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst401.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst401.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst401.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst401.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst401.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst401.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst401.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst401.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst401.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst401.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst401.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst401.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst401.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst401.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst401.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst401.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst401.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst401.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst401.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst401.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1046.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1046.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1046.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1046.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1046.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1046.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1046.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1046.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1046.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1046.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1046.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1046.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1046.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1046.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1046.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1046.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1046.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1046.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1046.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1046.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1046.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1046.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1046.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1046.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1046.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1046.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1046.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1046.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1046.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1046.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1046.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1046.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1046.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1394.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1394.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1394.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1394.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1394.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1394.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1394.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1394.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1394.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1394.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1394.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1394.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1394.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1394.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1394.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1394.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1394.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1394.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1394.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1394.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1394.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1394.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1394.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1394.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1394.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1394.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1394.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1394.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1394.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1394.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1394.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1394.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1394.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1629.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1629.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1629.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1629.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1629.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1629.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1629.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1629.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1629.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1629.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1629.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1629.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1629.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1629.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1629.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1629.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1629.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1629.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1629.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1629.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1629.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1629.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1629.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1629.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1629.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1629.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1629.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1629.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1629.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1629.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1629.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1629.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1629.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1862.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1862.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1862.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1862.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1862.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1862.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1862.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1862.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1862.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1862.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1862.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1862.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1862.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1862.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1862.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1862.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1862.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1862.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1862.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1862.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1862.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1862.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1862.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1862.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1862.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1862.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1862.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1862.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1862.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1862.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1862.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1862.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1862.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2210.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2210.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2210.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2210.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2210.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2210.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2210.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2210.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2210.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2210.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2210.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2210.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2210.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2210.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2210.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2210.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2210.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2210.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2210.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2210.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2210.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2210.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2210.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2210.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2210.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2210.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2210.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2210.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2210.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2210.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2210.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2210.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2210.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2250.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2250.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2250.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2250.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2250.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2250.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2250.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2250.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2250.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2250.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2250.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2250.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2250.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2250.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2250.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2250.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2250.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2250.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2250.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2250.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2250.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2250.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2250.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2250.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2250.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2250.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2250.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2250.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2250.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2250.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2250.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2250.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2250.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2461.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2461.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2461.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2461.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2461.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2461.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2461.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2461.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2461.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2461.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2461.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2461.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2461.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2461.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2461.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2461.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2461.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2461.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2461.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2461.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2461.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2461.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2461.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2461.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2461.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2461.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2461.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2461.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2461.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2461.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2461.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2461.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2461.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2711.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2711.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2711.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2711.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2711.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2711.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2711.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2711.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2711.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2711.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2711.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2711.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2711.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2711.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2711.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2711.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2711.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2711.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2711.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2711.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2711.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2711.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2711.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2711.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2711.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2711.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2711.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2711.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2711.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2711.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2711.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2711.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2711.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2731.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2731.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2731.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2731.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2731.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2731.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2731.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2731.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2731.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2731.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2731.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2731.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2731.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2731.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2731.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2731.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2731.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2731.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2731.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2731.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2731.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2731.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2731.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2731.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2731.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2731.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2731.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2731.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2731.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2731.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2731.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2731.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2731.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3889.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3889.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3889.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3889.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3889.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3889.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3889.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3889.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3889.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3889.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3889.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3889.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3889.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3889.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3889.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3889.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3889.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3889.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3889.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3889.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3889.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3889.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3889.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3889.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3889.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3889.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3889.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3889.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3889.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3889.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3889.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3889.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3889.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4378.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4378.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4378.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4378.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4378.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4378.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4378.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4378.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4378.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4378.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4378.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4378.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4378.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4378.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4378.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4378.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4378.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4378.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4378.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4378.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4378.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4378.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4378.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4378.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4378.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4378.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4378.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4378.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4378.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4378.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4378.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4378.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4378.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4426.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4426.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4426.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4426.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4426.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4426.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4426.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4426.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4426.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4426.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4426.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4426.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4426.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4426.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4426.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4426.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4426.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4426.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4426.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4426.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4426.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4426.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4426.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4426.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4426.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4426.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4426.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4426.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4426.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4426.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4426.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4426.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4426.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4977.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4977.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4977.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4977.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4977.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4977.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4977.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4977.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4977.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4977.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4977.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4977.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4977.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4977.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4977.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4977.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4977.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4977.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4977.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4977.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4977.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4977.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4977.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4977.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4977.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4977.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4977.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4977.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4977.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4977.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4977.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4977.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4977.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5226.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5226.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5226.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5226.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5226.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5226.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5226.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5226.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5226.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5226.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5226.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5226.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5226.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5226.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5226.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5226.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5226.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5226.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5226.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5226.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5226.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5226.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5226.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5226.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5226.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5226.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5226.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5226.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5226.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5226.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5226.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5226.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5226.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5524.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5524.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5524.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5524.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5524.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5524.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5524.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5524.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5524.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5524.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5524.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5524.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5524.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5524.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5524.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5524.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5524.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5524.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5524.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5524.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5524.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5524.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5524.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5524.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5524.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5524.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5524.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5524.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5524.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5524.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5524.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5524.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5524.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5707.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5707.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5707.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5707.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5707.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5707.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5707.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5707.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5707.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5707.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5707.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5707.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5707.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5707.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5707.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5707.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5707.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5707.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5707.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5707.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5707.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5707.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5707.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5707.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5707.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5707.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5707.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5707.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5707.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5707.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5707.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5707.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5707.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5931.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5931.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5931.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5931.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5931.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5931.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5931.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5931.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5931.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5931.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5931.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5931.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5931.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5931.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5931.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5931.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5931.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5931.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5931.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5931.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5931.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5931.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5931.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5931.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5931.xdly.x1i120 4.17 0.00 12.50 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5931.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5931.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5931.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5931.xdly.x1i175 8.33 0.00 25.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5931.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5931.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5931.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5931.xdly.xfc.x3 45.83 50.00 37.50 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5992.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5992.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5992.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5992.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5992.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5992.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5992.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5992.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5992.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5992.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5992.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5992.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5992.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5992.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5992.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5992.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5992.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5992.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5992.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5992.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5992.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5992.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5992.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5992.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5992.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5992.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5992.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5992.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5992.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5992.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5992.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5992.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5992.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6070.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6070.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6070.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6070.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6070.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6070.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6070.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6070.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6070.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6070.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6070.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6070.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6070.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6070.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6070.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6070.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6070.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6070.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6070.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6070.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6070.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6070.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6070.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6070.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6070.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6070.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6070.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6070.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6070.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6070.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6070.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6070.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6070.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6198.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6198.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6198.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6198.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6198.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6198.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6198.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6198.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6198.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6198.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6198.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6198.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6198.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6198.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6198.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6198.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6198.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6198.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6198.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6198.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6198.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6198.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6198.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6198.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6198.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6198.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6198.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6198.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6198.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6198.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6198.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6198.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6198.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6411.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6411.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6411.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6411.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6411.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6411.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6411.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6411.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6411.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6411.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6411.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6411.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6411.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6411.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6411.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6411.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6411.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6411.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6411.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6411.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6411.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6411.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6411.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6411.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6411.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6411.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6411.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6411.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6411.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6411.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6411.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6411.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6411.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6742.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6742.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6742.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6742.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6742.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6742.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6742.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6742.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6742.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6742.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6742.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6742.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6742.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6742.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6742.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6742.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6742.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6742.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6742.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6742.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6742.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6742.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6742.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6742.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6742.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6742.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6742.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6742.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6742.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6742.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6742.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6742.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6742.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7211.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7211.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7211.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7211.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7211.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7211.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7211.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7211.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7211.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7211.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7211.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7211.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7211.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7211.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7211.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7211.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7211.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7211.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7211.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7211.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7211.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7211.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7211.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7211.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7211.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7211.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7211.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7211.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7211.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7211.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7211.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7211.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7211.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7238.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7238.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7238.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7238.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7238.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7238.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7238.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7238.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7238.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7238.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7238.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7238.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7238.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7238.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7238.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7238.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7238.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7238.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7238.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7238.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7238.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7238.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7238.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7238.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7238.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7238.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7238.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7238.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7238.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7238.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7238.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7238.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7238.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7340.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7340.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7340.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7340.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7340.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7340.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7340.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7340.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7340.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7340.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7340.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7340.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7340.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7340.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7340.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7340.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7340.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7340.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7340.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7340.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7340.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7340.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7340.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7340.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7340.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7340.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7340.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7340.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7340.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7340.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7340.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7340.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7340.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7653.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7653.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7653.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7653.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7653.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7653.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7653.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7653.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7653.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7653.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7653.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7653.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7653.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7653.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7653.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7653.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7653.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7653.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7653.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7653.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7653.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7653.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7653.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7653.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7653.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7653.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7653.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7653.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7653.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7653.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7653.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7653.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7653.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7801.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7801.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7801.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7801.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7801.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7801.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7801.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7801.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7801.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7801.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7801.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7801.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7801.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7801.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7801.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7801.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7801.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7801.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7801.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7801.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7801.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7801.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7801.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7801.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7801.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7801.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7801.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7801.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7801.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7801.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7801.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7801.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7801.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7986.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7986.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7986.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7986.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7986.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7986.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7986.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7986.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7986.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7986.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7986.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7986.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7986.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7986.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7986.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7986.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7986.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7986.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7986.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7986.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7986.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7986.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7986.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7986.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7986.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7986.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7986.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7986.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7986.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7986.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7986.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7986.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7986.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8251.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8251.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8251.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8251.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8251.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8251.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8251.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8251.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8251.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8251.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8251.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8251.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8251.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8251.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8251.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8251.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8251.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8251.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8251.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8251.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8251.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8251.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8251.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8251.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8251.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8251.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8251.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8251.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8251.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8251.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8251.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8251.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8251.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9148.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9148.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9148.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9148.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9148.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9148.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9148.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9148.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9148.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9148.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9148.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9148.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9148.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9148.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9148.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9148.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9148.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9148.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9148.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9148.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9148.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9148.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9148.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9148.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9148.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9148.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9148.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9148.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9148.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9148.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9148.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9148.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9148.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9164.xdly.x1i27 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9164.xdly.x1i28 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9164.xdly.x1i29 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9164.xdly.x1i30 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9164.xdly.x1i31 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9164.xdly.x1i36 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9164.xdly.x1i40 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9164.xdly.x1i45 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9164.xdly.x1i49 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9164.xdly.x1i50 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9164.xdly.x1i51 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9164.xdly.x1i80 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9164.xdly.x1i81 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9164.xdly.x1i82 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9164.xdly.x1i83 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9164.xdly.x1i84 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9164.xdly.x1i85 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9164.xdly.x1i89 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9164.xdly.x1i93 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9164.xdly.x1i96 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9164.xdly.x1i103 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9164.xdly.x1i108 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9164.xdly.x1i112 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9164.xdly.x1i117 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9164.xdly.x1i120 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9164.xdly.x1i121 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9164.xdly.x1i122 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9164.xdly.x1i123 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9164.xdly.x1i175 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9164.xdly.x1i177 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9164.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9164.xdly.x1i193 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9164.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9178.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9178.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9178.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9178.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9178.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9178.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9178.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9178.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9178.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9178.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9178.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9178.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9178.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9178.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9178.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9178.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9178.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9178.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9178.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9178.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9178.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9178.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9178.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9178.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9178.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9178.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9178.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9178.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9178.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9178.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9178.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9178.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9178.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9403.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9403.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9403.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9403.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9403.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9403.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9403.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9403.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9403.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9403.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9403.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9403.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9403.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9403.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9403.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9403.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9403.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9403.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9403.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9403.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9403.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9403.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9403.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9403.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9403.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9403.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9403.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9403.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9403.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9403.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9403.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9403.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9403.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9425.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9425.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9425.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9425.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9425.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9425.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9425.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9425.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9425.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9425.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9425.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9425.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9425.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9425.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9425.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9425.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9425.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9425.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9425.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9425.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9425.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9425.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9425.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9425.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9425.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9425.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9425.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9425.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9425.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9425.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9425.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9425.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9425.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9788.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9788.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9788.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9788.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9788.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9788.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9788.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9788.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9788.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9788.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9788.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9788.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9788.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9788.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9788.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9788.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9788.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9788.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9788.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9788.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9788.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9788.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9788.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9788.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9788.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9788.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9788.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9788.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9788.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9788.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9788.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9788.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9788.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9915.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9915.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9915.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9915.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9915.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9915.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9915.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9915.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9915.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9915.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9915.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9915.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9915.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9915.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9915.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9915.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9915.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9915.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9915.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9915.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9915.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9915.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9915.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9915.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9915.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9915.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9915.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9915.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9915.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9915.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9915.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9915.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9915.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10217.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10217.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10217.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10217.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10217.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10217.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10217.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10217.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10217.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10217.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10217.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10217.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10217.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10217.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10217.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10217.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10217.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10217.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10217.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10217.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10217.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10217.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10217.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10217.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10217.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10217.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10217.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10217.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10217.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10217.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10217.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10217.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10217.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11361.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11361.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11361.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11361.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11361.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11361.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11361.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11361.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11361.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11361.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11361.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11361.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11361.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11361.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11361.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11361.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11361.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11361.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11361.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11361.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11361.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11361.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11361.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11361.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11361.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11361.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11361.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11361.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11361.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11361.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11361.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11361.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11361.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11605.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11605.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11605.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11605.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11605.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11605.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11605.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11605.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11605.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11605.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11605.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11605.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11605.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11605.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11605.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11605.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11605.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11605.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11605.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11605.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11605.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11605.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11605.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11605.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11605.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11605.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11605.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11605.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11605.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11605.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11605.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11605.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11605.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11664.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11664.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11664.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11664.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11664.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11664.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11664.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11664.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11664.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11664.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11664.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11664.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11664.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11664.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11664.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11664.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11664.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11664.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11664.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11664.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11664.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11664.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11664.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11664.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11664.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11664.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11664.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11664.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11664.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11664.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11664.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11664.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11664.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11943.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11943.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11943.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11943.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11943.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11943.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11943.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11943.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11943.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11943.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11943.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11943.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11943.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11943.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11943.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11943.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11943.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11943.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11943.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11943.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11943.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11943.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11943.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11943.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11943.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11943.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11943.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11943.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11943.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11943.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11943.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11943.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11943.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst100.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst100.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst100.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst100.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst100.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst100.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst100.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst100.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst100.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst100.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst100.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst100.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst100.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst100.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst100.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst100.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst100.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst100.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst100.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst100.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst100.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst100.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst100.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst100.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst100.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst100.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst100.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst100.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst100.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst100.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst100.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst100.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst100.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst89.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst89.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst89.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst89.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst89.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst89.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst89.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst89.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst89.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst89.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst89.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst89.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst89.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst89.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst89.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst89.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst89.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst89.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst89.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst89.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst89.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst89.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst89.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst89.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst89.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst89.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst89.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst89.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst89.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst89.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst89.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst89.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst89.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst254.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst254.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst254.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst254.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst254.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst254.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst254.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst254.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst254.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst254.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst254.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst254.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst254.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst254.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst254.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst254.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst254.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst254.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst254.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst254.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst254.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst254.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst254.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst254.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst254.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst254.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst254.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst254.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst254.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst254.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst254.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst254.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst254.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst382.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst382.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst382.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst382.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst382.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst382.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst382.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst382.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst382.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst382.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst382.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst382.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst382.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst382.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst382.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst382.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst382.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst382.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst382.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst382.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst382.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst382.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst382.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst382.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst382.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst382.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst382.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst382.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst382.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst382.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst382.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst382.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst382.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst401.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst401.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst401.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst401.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst401.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst401.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst401.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst401.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst401.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst401.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst401.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst401.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst401.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst401.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst401.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst401.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst401.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst401.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst401.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst401.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst401.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst401.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst401.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst401.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst401.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst401.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst401.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst401.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst401.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst401.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst401.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst401.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst401.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1046.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1046.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1046.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1046.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1046.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1046.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1046.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1046.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1046.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1046.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1046.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1046.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1046.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1046.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1046.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1046.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1046.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1046.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1046.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1046.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1046.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1046.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1046.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1046.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1046.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1046.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1046.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1046.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1046.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1046.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1046.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1046.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1046.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1394.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1394.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1394.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1394.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1394.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1394.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1394.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1394.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1394.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1394.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1394.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1394.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1394.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1394.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1394.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1394.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1394.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1394.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1394.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1394.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1394.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1394.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1394.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1394.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1394.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1394.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1394.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1394.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1394.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1394.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1394.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1394.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1394.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1629.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1629.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1629.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1629.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1629.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1629.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1629.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1629.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1629.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1629.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1629.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1629.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1629.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1629.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1629.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1629.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1629.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1629.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1629.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1629.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1629.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1629.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1629.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1629.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1629.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1629.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1629.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1629.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1629.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1629.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1629.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1629.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1629.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1862.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1862.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1862.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1862.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1862.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1862.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1862.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1862.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1862.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1862.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1862.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1862.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1862.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1862.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1862.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1862.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1862.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1862.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1862.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1862.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1862.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1862.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1862.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1862.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1862.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1862.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1862.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1862.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1862.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1862.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1862.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1862.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1862.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2210.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2210.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2210.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2210.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2210.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2210.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2210.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2210.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2210.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2210.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2210.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2210.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2210.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2210.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2210.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2210.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2210.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2210.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2210.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2210.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2210.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2210.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2210.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2210.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2210.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2210.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2210.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2210.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2210.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2210.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2210.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2210.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2210.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2250.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2250.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2250.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2250.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2250.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2250.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2250.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2250.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2250.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2250.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2250.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2250.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2250.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2250.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2250.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2250.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2250.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2250.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2250.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2250.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2250.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2250.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2250.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2250.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2250.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2250.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2250.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2250.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2250.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2250.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2250.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2250.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2250.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2461.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2461.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2461.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2461.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2461.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2461.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2461.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2461.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2461.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2461.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2461.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2461.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2461.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2461.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2461.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2461.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2461.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2461.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2461.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2461.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2461.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2461.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2461.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2461.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2461.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2461.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2461.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2461.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2461.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2461.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2461.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2461.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2461.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2711.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2711.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2711.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2711.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2711.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2711.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2711.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2711.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2711.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2711.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2711.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2711.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2711.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2711.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2711.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2711.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2711.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2711.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2711.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2711.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2711.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2711.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2711.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2711.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2711.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2711.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2711.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2711.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2711.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2711.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2711.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2711.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2711.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2731.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2731.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2731.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2731.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2731.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2731.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2731.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2731.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2731.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2731.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2731.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2731.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2731.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2731.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2731.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2731.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2731.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2731.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2731.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2731.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2731.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2731.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2731.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2731.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2731.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2731.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2731.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2731.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2731.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2731.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2731.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2731.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2731.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3889.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3889.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3889.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3889.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3889.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3889.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3889.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3889.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3889.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3889.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3889.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3889.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3889.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3889.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3889.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3889.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3889.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3889.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3889.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3889.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3889.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3889.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3889.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3889.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3889.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3889.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3889.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3889.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3889.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3889.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3889.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3889.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3889.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4378.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4378.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4378.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4378.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4378.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4378.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4378.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4378.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4378.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4378.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4378.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4378.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4378.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4378.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4378.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4378.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4378.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4378.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4378.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4378.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4378.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4378.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4378.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4378.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4378.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4378.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4378.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4378.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4378.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4378.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4378.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4378.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4378.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4426.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4426.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4426.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4426.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4426.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4426.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4426.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4426.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4426.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4426.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4426.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4426.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4426.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4426.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4426.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4426.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4426.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4426.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4426.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4426.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4426.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4426.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4426.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4426.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4426.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4426.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4426.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4426.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4426.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4426.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4426.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4426.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4426.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4977.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4977.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4977.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4977.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4977.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4977.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4977.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4977.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4977.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4977.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4977.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4977.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4977.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4977.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4977.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4977.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4977.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4977.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4977.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4977.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4977.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4977.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4977.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4977.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4977.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4977.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4977.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4977.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4977.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4977.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4977.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4977.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4977.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5226.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5226.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5226.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5226.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5226.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5226.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5226.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5226.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5226.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5226.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5226.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5226.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5226.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5226.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5226.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5226.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5226.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5226.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5226.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5226.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5226.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5226.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5226.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5226.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5226.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5226.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5226.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5226.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5226.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5226.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5226.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5226.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5226.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5524.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5524.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5524.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5524.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5524.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5524.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5524.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5524.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5524.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5524.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5524.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5524.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5524.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5524.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5524.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5524.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5524.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5524.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5524.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5524.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5524.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5524.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5524.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5524.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5524.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5524.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5524.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5524.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5524.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5524.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5524.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5524.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5524.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5707.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5707.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5707.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5707.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5707.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5707.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5707.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5707.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5707.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5707.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5707.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5707.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5707.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5707.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5707.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5707.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5707.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5707.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5707.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5707.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5707.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5707.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5707.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5707.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5707.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5707.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5707.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5707.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5707.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5707.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5707.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5707.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5707.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5931.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5931.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5931.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5931.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5931.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5931.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5931.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5931.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5931.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5931.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5931.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5931.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5931.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5931.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5931.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5931.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5931.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5931.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5931.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5931.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5931.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5931.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5931.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5931.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5931.xdly.x1i120 4.17 0.00 12.50 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5931.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5931.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5931.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5931.xdly.x1i175 8.33 0.00 25.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5931.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5931.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5931.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5931.xdly.xfc.x3 45.83 50.00 37.50 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5992.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5992.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5992.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5992.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5992.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5992.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5992.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5992.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5992.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5992.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5992.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5992.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5992.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5992.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5992.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5992.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5992.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5992.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5992.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5992.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5992.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5992.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5992.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5992.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5992.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5992.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5992.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5992.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5992.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5992.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5992.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5992.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5992.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6070.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6070.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6070.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6070.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6070.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6070.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6070.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6070.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6070.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6070.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6070.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6070.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6070.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6070.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6070.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6070.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6070.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6070.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6070.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6070.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6070.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6070.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6070.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6070.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6070.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6070.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6070.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6070.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6070.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6070.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6070.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6070.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6070.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6198.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6198.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6198.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6198.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6198.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6198.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6198.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6198.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6198.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6198.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6198.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6198.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6198.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6198.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6198.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6198.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6198.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6198.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6198.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6198.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6198.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6198.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6198.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6198.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6198.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6198.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6198.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6198.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6198.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6198.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6198.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6198.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6198.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6411.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6411.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6411.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6411.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6411.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6411.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6411.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6411.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6411.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6411.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6411.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6411.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6411.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6411.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6411.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6411.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6411.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6411.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6411.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6411.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6411.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6411.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6411.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6411.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6411.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6411.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6411.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6411.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6411.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6411.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6411.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6411.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6411.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6742.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6742.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6742.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6742.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6742.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6742.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6742.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6742.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6742.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6742.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6742.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6742.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6742.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6742.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6742.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6742.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6742.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6742.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6742.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6742.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6742.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6742.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6742.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6742.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6742.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6742.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6742.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6742.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6742.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6742.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6742.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6742.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6742.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7211.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7211.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7211.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7211.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7211.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7211.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7211.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7211.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7211.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7211.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7211.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7211.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7211.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7211.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7211.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7211.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7211.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7211.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7211.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7211.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7211.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7211.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7211.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7211.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7211.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7211.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7211.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7211.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7211.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7211.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7211.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7211.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7211.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7238.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7238.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7238.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7238.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7238.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7238.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7238.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7238.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7238.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7238.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7238.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7238.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7238.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7238.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7238.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7238.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7238.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7238.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7238.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7238.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7238.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7238.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7238.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7238.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7238.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7238.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7238.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7238.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7238.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7238.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7238.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7238.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7238.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7340.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7340.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7340.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7340.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7340.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7340.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7340.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7340.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7340.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7340.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7340.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7340.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7340.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7340.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7340.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7340.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7340.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7340.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7340.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7340.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7340.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7340.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7340.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7340.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7340.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7340.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7340.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7340.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7340.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7340.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7340.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7340.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7340.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7653.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7653.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7653.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7653.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7653.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7653.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7653.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7653.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7653.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7653.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7653.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7653.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7653.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7653.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7653.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7653.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7653.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7653.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7653.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7653.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7653.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7653.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7653.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7653.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7653.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7653.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7653.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7653.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7653.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7653.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7653.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7653.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7653.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7801.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7801.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7801.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7801.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7801.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7801.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7801.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7801.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7801.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7801.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7801.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7801.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7801.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7801.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7801.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7801.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7801.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7801.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7801.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7801.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7801.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7801.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7801.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7801.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7801.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7801.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7801.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7801.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7801.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7801.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7801.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7801.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7801.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7986.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7986.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7986.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7986.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7986.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7986.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7986.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7986.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7986.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7986.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7986.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7986.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7986.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7986.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7986.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7986.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7986.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7986.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7986.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7986.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7986.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7986.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7986.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7986.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7986.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7986.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7986.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7986.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7986.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7986.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7986.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7986.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7986.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8251.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8251.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8251.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8251.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8251.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8251.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8251.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8251.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8251.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8251.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8251.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8251.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8251.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8251.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8251.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8251.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8251.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8251.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8251.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8251.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8251.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8251.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8251.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8251.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8251.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8251.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8251.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8251.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8251.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8251.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8251.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8251.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8251.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9148.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9148.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9148.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9148.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9148.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9148.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9148.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9148.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9148.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9148.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9148.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9148.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9148.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9148.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9148.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9148.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9148.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9148.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9148.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9148.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9148.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9148.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9148.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9148.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9148.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9148.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9148.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9148.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9148.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9148.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9148.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9148.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9148.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9164.xdly.x1i27 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9164.xdly.x1i28 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9164.xdly.x1i29 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9164.xdly.x1i30 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9164.xdly.x1i31 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9164.xdly.x1i36 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9164.xdly.x1i40 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9164.xdly.x1i45 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9164.xdly.x1i49 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9164.xdly.x1i50 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9164.xdly.x1i51 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9164.xdly.x1i80 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9164.xdly.x1i81 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9164.xdly.x1i82 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9164.xdly.x1i83 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9164.xdly.x1i84 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9164.xdly.x1i85 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9164.xdly.x1i89 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9164.xdly.x1i93 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9164.xdly.x1i96 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9164.xdly.x1i103 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9164.xdly.x1i108 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9164.xdly.x1i112 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9164.xdly.x1i117 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9164.xdly.x1i120 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9164.xdly.x1i121 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9164.xdly.x1i122 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9164.xdly.x1i123 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9164.xdly.x1i175 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9164.xdly.x1i177 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9164.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9164.xdly.x1i193 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9164.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9178.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9178.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9178.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9178.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9178.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9178.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9178.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9178.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9178.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9178.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9178.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9178.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9178.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9178.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9178.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9178.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9178.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9178.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9178.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9178.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9178.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9178.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9178.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9178.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9178.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9178.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9178.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9178.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9178.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9178.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9178.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9178.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9178.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9403.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9403.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9403.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9403.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9403.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9403.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9403.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9403.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9403.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9403.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9403.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9403.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9403.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9403.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9403.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9403.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9403.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9403.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9403.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9403.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9403.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9403.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9403.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9403.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9403.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9403.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9403.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9403.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9403.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9403.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9403.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9403.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9403.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9425.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9425.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9425.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9425.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9425.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9425.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9425.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9425.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9425.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9425.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9425.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9425.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9425.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9425.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9425.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9425.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9425.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9425.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9425.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9425.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9425.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9425.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9425.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9425.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9425.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9425.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9425.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9425.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9425.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9425.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9425.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9425.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9425.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9788.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9788.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9788.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9788.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9788.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9788.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9788.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9788.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9788.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9788.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9788.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9788.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9788.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9788.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9788.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9788.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9788.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9788.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9788.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9788.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9788.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9788.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9788.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9788.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9788.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9788.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9788.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9788.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9788.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9788.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9788.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9788.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9788.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9915.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9915.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9915.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9915.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9915.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9915.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9915.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9915.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9915.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9915.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9915.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9915.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9915.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9915.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9915.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9915.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9915.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9915.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9915.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9915.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9915.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9915.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9915.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9915.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9915.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9915.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9915.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9915.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9915.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9915.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9915.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9915.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9915.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10217.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10217.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10217.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10217.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10217.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10217.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10217.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10217.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10217.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10217.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10217.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10217.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10217.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10217.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10217.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10217.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10217.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10217.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10217.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10217.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10217.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10217.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10217.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10217.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10217.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10217.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10217.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10217.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10217.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10217.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10217.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10217.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10217.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11361.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11361.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11361.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11361.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11361.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11361.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11361.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11361.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11361.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11361.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11361.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11361.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11361.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11361.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11361.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11361.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11361.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11361.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11361.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11361.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11361.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11361.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11361.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11361.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11361.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11361.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11361.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11361.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11361.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11361.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11361.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11361.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11361.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11605.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11605.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11605.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11605.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11605.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11605.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11605.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11605.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11605.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11605.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11605.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11605.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11605.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11605.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11605.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11605.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11605.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11605.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11605.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11605.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11605.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11605.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11605.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11605.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11605.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11605.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11605.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11605.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11605.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11605.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11605.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11605.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11605.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11664.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11664.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11664.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11664.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11664.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11664.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11664.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11664.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11664.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11664.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11664.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11664.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11664.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11664.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11664.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11664.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11664.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11664.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11664.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11664.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11664.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11664.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11664.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11664.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11664.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11664.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11664.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11664.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11664.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11664.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11664.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11664.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11664.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11943.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11943.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11943.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11943.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11943.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11943.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11943.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11943.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11943.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11943.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11943.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11943.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11943.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11943.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11943.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11943.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11943.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11943.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11943.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11943.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11943.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11943.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11943.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11943.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11943.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11943.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11943.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11943.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11943.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11943.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11943.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11943.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11943.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst100.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst100.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst100.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst100.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst100.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst100.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst100.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst100.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst100.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst100.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst100.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst100.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst100.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst100.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst100.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst100.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst100.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst100.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst100.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst100.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst100.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst100.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst100.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst100.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst100.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst100.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst100.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst100.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst100.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst100.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst100.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst100.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst100.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst89.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst89.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst89.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst89.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst89.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst89.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst89.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst89.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst89.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst89.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst89.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst89.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst89.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst89.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst89.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst89.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst89.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst89.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst89.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst89.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst89.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst89.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst89.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst89.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst89.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst89.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst89.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst89.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst89.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst89.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst89.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst89.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst89.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst254.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst254.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst254.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst254.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst254.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst254.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst254.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst254.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst254.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst254.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst254.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst254.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst254.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst254.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst254.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst254.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst254.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst254.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst254.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst254.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst254.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst254.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst254.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst254.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst254.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst254.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst254.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst254.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst254.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst254.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst254.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst254.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst254.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst382.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst382.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst382.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst382.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst382.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst382.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst382.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst382.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst382.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst382.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst382.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst382.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst382.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst382.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst382.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst382.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst382.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst382.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst382.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst382.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst382.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst382.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst382.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst382.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst382.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst382.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst382.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst382.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst382.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst382.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst382.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst382.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst382.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst401.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst401.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst401.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst401.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst401.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst401.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst401.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst401.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst401.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst401.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst401.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst401.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst401.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst401.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst401.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst401.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst401.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst401.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst401.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst401.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst401.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst401.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst401.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst401.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst401.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst401.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst401.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst401.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst401.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst401.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst401.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst401.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst401.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1046.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1046.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1046.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1046.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1046.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1046.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1046.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1046.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1046.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1046.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1046.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1046.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1046.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1046.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1046.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1046.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1046.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1046.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1046.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1046.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1046.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1046.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1046.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1046.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1046.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1046.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1046.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1046.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1046.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1046.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1046.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1046.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1046.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1394.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1394.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1394.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1394.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1394.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1394.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1394.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1394.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1394.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1394.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1394.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1394.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1394.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1394.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1394.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1394.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1394.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1394.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1394.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1394.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1394.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1394.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1394.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1394.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1394.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1394.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1394.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1394.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1394.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1394.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1394.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1394.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1394.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1629.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1629.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1629.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1629.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1629.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1629.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1629.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1629.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1629.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1629.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1629.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1629.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1629.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1629.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1629.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1629.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1629.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1629.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1629.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1629.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1629.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1629.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1629.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1629.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1629.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1629.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1629.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1629.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1629.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1629.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1629.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1629.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1629.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1862.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1862.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1862.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1862.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1862.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1862.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1862.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1862.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1862.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1862.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1862.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1862.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1862.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1862.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1862.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1862.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1862.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1862.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1862.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1862.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1862.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1862.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1862.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1862.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1862.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1862.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1862.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1862.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1862.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1862.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1862.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1862.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1862.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2210.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2210.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2210.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2210.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2210.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2210.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2210.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2210.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2210.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2210.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2210.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2210.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2210.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2210.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2210.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2210.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2210.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2210.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2210.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2210.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2210.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2210.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2210.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2210.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2210.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2210.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2210.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2210.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2210.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2210.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2210.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2210.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2210.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2250.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2250.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2250.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2250.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2250.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2250.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2250.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2250.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2250.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2250.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2250.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2250.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2250.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2250.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2250.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2250.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2250.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2250.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2250.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2250.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2250.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2250.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2250.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2250.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2250.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2250.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2250.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2250.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2250.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2250.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2250.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2250.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2250.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2461.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2461.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2461.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2461.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2461.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2461.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2461.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2461.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2461.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2461.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2461.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2461.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2461.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2461.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2461.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2461.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2461.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2461.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2461.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2461.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2461.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2461.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2461.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2461.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2461.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2461.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2461.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2461.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2461.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2461.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2461.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2461.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2461.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2711.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2711.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2711.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2711.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2711.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2711.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2711.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2711.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2711.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2711.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2711.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2711.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2711.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2711.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2711.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2711.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2711.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2711.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2711.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2711.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2711.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2711.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2711.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2711.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2711.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2711.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2711.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2711.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2711.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2711.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2711.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2711.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2711.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2731.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2731.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2731.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2731.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2731.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2731.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2731.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2731.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2731.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2731.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2731.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2731.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2731.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2731.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2731.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2731.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2731.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2731.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2731.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2731.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2731.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2731.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2731.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2731.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2731.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2731.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2731.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2731.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2731.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2731.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2731.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2731.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2731.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3889.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3889.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3889.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3889.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3889.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3889.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3889.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3889.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3889.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3889.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3889.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3889.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3889.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3889.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3889.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3889.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3889.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3889.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3889.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3889.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3889.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3889.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3889.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3889.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3889.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3889.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3889.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3889.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3889.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3889.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3889.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3889.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3889.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4378.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4378.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4378.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4378.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4378.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4378.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4378.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4378.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4378.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4378.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4378.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4378.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4378.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4378.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4378.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4378.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4378.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4378.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4378.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4378.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4378.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4378.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4378.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4378.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4378.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4378.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4378.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4378.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4378.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4378.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4378.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4378.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4378.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4426.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4426.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4426.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4426.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4426.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4426.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4426.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4426.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4426.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4426.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4426.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4426.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4426.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4426.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4426.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4426.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4426.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4426.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4426.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4426.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4426.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4426.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4426.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4426.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4426.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4426.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4426.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4426.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4426.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4426.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4426.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4426.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4426.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4977.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4977.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4977.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4977.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4977.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4977.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4977.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4977.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4977.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4977.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4977.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4977.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4977.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4977.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4977.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4977.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4977.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4977.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4977.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4977.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4977.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4977.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4977.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4977.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4977.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4977.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4977.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4977.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4977.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4977.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4977.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4977.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4977.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5226.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5226.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5226.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5226.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5226.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5226.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5226.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5226.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5226.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5226.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5226.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5226.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5226.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5226.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5226.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5226.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5226.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5226.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5226.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5226.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5226.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5226.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5226.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5226.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5226.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5226.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5226.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5226.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5226.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5226.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5226.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5226.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5226.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5524.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5524.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5524.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5524.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5524.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5524.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5524.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5524.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5524.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5524.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5524.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5524.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5524.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5524.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5524.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5524.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5524.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5524.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5524.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5524.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5524.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5524.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5524.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5524.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5524.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5524.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5524.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5524.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5524.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5524.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5524.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5524.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5524.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5707.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5707.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5707.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5707.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5707.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5707.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5707.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5707.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5707.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5707.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5707.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5707.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5707.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5707.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5707.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5707.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5707.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5707.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5707.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5707.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5707.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5707.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5707.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5707.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5707.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5707.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5707.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5707.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5707.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5707.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5707.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5707.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5707.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5931.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5931.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5931.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5931.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5931.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5931.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5931.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5931.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5931.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5931.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5931.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5931.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5931.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5931.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5931.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5931.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5931.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5931.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5931.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5931.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5931.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5931.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5931.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5931.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5931.xdly.x1i120 4.17 0.00 12.50 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5931.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5931.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5931.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5931.xdly.x1i175 8.33 0.00 25.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5931.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5931.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5931.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5931.xdly.xfc.x3 45.83 50.00 37.50 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5992.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5992.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5992.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5992.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5992.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5992.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5992.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5992.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5992.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5992.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5992.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5992.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5992.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5992.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5992.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5992.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5992.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5992.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5992.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5992.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5992.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5992.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5992.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5992.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5992.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5992.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5992.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5992.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5992.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5992.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5992.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5992.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5992.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6070.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6070.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6070.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6070.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6070.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6070.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6070.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6070.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6070.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6070.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6070.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6070.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6070.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6070.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6070.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6070.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6070.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6070.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6070.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6070.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6070.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6070.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6070.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6070.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6070.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6070.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6070.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6070.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6070.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6070.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6070.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6070.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6070.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6198.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6198.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6198.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6198.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6198.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6198.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6198.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6198.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6198.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6198.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6198.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6198.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6198.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6198.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6198.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6198.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6198.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6198.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6198.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6198.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6198.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6198.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6198.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6198.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6198.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6198.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6198.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6198.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6198.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6198.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6198.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6198.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6198.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6411.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6411.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6411.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6411.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6411.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6411.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6411.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6411.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6411.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6411.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6411.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6411.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6411.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6411.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6411.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6411.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6411.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6411.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6411.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6411.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6411.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6411.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6411.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6411.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6411.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6411.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6411.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6411.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6411.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6411.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6411.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6411.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6411.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6742.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6742.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6742.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6742.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6742.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6742.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6742.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6742.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6742.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6742.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6742.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6742.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6742.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6742.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6742.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6742.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6742.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6742.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6742.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6742.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6742.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6742.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6742.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6742.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6742.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6742.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6742.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6742.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6742.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6742.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6742.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6742.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6742.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7211.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7211.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7211.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7211.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7211.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7211.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7211.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7211.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7211.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7211.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7211.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7211.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7211.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7211.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7211.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7211.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7211.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7211.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7211.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7211.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7211.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7211.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7211.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7211.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7211.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7211.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7211.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7211.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7211.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7211.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7211.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7211.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7211.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7238.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7238.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7238.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7238.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7238.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7238.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7238.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7238.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7238.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7238.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7238.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7238.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7238.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7238.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7238.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7238.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7238.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7238.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7238.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7238.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7238.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7238.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7238.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7238.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7238.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7238.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7238.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7238.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7238.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7238.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7238.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7238.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7238.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7340.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7340.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7340.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7340.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7340.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7340.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7340.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7340.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7340.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7340.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7340.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7340.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7340.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7340.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7340.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7340.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7340.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7340.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7340.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7340.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7340.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7340.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7340.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7340.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7340.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7340.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7340.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7340.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7340.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7340.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7340.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7340.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7340.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7653.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7653.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7653.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7653.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7653.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7653.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7653.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7653.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7653.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7653.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7653.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7653.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7653.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7653.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7653.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7653.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7653.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7653.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7653.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7653.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7653.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7653.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7653.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7653.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7653.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7653.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7653.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7653.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7653.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7653.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7653.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7653.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7653.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7801.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7801.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7801.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7801.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7801.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7801.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7801.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7801.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7801.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7801.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7801.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7801.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7801.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7801.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7801.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7801.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7801.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7801.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7801.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7801.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7801.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7801.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7801.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7801.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7801.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7801.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7801.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7801.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7801.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7801.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7801.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7801.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7801.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7986.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7986.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7986.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7986.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7986.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7986.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7986.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7986.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7986.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7986.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7986.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7986.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7986.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7986.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7986.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7986.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7986.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7986.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7986.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7986.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7986.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7986.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7986.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7986.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7986.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7986.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7986.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7986.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7986.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7986.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7986.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7986.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7986.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8251.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8251.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8251.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8251.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8251.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8251.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8251.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8251.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8251.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8251.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8251.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8251.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8251.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8251.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8251.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8251.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8251.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8251.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8251.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8251.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8251.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8251.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8251.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8251.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8251.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8251.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8251.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8251.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8251.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8251.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8251.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8251.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8251.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9148.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9148.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9148.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9148.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9148.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9148.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9148.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9148.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9148.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9148.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9148.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9148.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9148.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9148.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9148.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9148.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9148.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9148.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9148.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9148.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9148.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9148.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9148.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9148.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9148.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9148.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9148.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9148.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9148.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9148.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9148.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9148.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9148.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9164.xdly.x1i27 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9164.xdly.x1i28 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9164.xdly.x1i29 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9164.xdly.x1i30 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9164.xdly.x1i31 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9164.xdly.x1i36 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9164.xdly.x1i40 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9164.xdly.x1i45 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9164.xdly.x1i49 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9164.xdly.x1i50 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9164.xdly.x1i51 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9164.xdly.x1i80 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9164.xdly.x1i81 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9164.xdly.x1i82 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9164.xdly.x1i83 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9164.xdly.x1i84 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9164.xdly.x1i85 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9164.xdly.x1i89 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9164.xdly.x1i93 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9164.xdly.x1i96 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9164.xdly.x1i103 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9164.xdly.x1i108 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9164.xdly.x1i112 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9164.xdly.x1i117 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9164.xdly.x1i120 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9164.xdly.x1i121 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9164.xdly.x1i122 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9164.xdly.x1i123 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9164.xdly.x1i175 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9164.xdly.x1i177 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9164.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9164.xdly.x1i193 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9164.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9178.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9178.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9178.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9178.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9178.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9178.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9178.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9178.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9178.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9178.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9178.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9178.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9178.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9178.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9178.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9178.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9178.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9178.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9178.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9178.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9178.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9178.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9178.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9178.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9178.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9178.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9178.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9178.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9178.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9178.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9178.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9178.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9178.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9403.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9403.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9403.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9403.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9403.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9403.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9403.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9403.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9403.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9403.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9403.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9403.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9403.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9403.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9403.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9403.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9403.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9403.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9403.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9403.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9403.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9403.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9403.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9403.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9403.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9403.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9403.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9403.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9403.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9403.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9403.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9403.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9403.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9425.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9425.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9425.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9425.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9425.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9425.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9425.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9425.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9425.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9425.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9425.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9425.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9425.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9425.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9425.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9425.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9425.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9425.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9425.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9425.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9425.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9425.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9425.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9425.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9425.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9425.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9425.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9425.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9425.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9425.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9425.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9425.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9425.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9788.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9788.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9788.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9788.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9788.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9788.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9788.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9788.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9788.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9788.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9788.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9788.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9788.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9788.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9788.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9788.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9788.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9788.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9788.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9788.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9788.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9788.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9788.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9788.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9788.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9788.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9788.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9788.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9788.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9788.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9788.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9788.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9788.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9915.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9915.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9915.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9915.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9915.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9915.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9915.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9915.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9915.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9915.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9915.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9915.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9915.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9915.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9915.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9915.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9915.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9915.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9915.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9915.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9915.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9915.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9915.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9915.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9915.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9915.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9915.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9915.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9915.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9915.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9915.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9915.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9915.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10217.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10217.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10217.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10217.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10217.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10217.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10217.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10217.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10217.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10217.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10217.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10217.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10217.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10217.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10217.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10217.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10217.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10217.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10217.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10217.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10217.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10217.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10217.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10217.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10217.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10217.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10217.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10217.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10217.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10217.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10217.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10217.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10217.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11361.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11361.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11361.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11361.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11361.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11361.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11361.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11361.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11361.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11361.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11361.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11361.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11361.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11361.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11361.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11361.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11361.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11361.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11361.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11361.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11361.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11361.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11361.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11361.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11361.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11361.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11361.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11361.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11361.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11361.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11361.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11361.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11361.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11605.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11605.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11605.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11605.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11605.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11605.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11605.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11605.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11605.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11605.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11605.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11605.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11605.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11605.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11605.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11605.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11605.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11605.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11605.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11605.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11605.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11605.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11605.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11605.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11605.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11605.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11605.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11605.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11605.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11605.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11605.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11605.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11605.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11664.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11664.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11664.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11664.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11664.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11664.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11664.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11664.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11664.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11664.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11664.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11664.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11664.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11664.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11664.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11664.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11664.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11664.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11664.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11664.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11664.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11664.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11664.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11664.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11664.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11664.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11664.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11664.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11664.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11664.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11664.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11664.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11664.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11943.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11943.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11943.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11943.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11943.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11943.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11943.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11943.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11943.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11943.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11943.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11943.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11943.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11943.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11943.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11943.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11943.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11943.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11943.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11943.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11943.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11943.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11943.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11943.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11943.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11943.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11943.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11943.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11943.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11943.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11943.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11943.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11943.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst100.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst100.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst100.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst100.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst100.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst100.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst100.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst100.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst100.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst100.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst100.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst100.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst100.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst100.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst100.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst100.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst100.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst100.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst100.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst100.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst100.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst100.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst100.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst100.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst100.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst100.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst100.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst100.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst100.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst100.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst100.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst100.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst100.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst89.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst89.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst89.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst89.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst89.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst89.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst89.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst89.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst89.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst89.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst89.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst89.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst89.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst89.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst89.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst89.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst89.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst89.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst89.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst89.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst89.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst89.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst89.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst89.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst89.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst89.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst89.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst89.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst89.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst89.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst89.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst89.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst89.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst254.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst254.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst254.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst254.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst254.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst254.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst254.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst254.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst254.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst254.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst254.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst254.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst254.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst254.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst254.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst254.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst254.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst254.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst254.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst254.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst254.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst254.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst254.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst254.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst254.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst254.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst254.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst254.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst254.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst254.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst254.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst254.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst254.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst382.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst382.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst382.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst382.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst382.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst382.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst382.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst382.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst382.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst382.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst382.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst382.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst382.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst382.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst382.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst382.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst382.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst382.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst382.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst382.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst382.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst382.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst382.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst382.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst382.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst382.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst382.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst382.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst382.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst382.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst382.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst382.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst382.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst401.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst401.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst401.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst401.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst401.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst401.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst401.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst401.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst401.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst401.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst401.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst401.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst401.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst401.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst401.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst401.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst401.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst401.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst401.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst401.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst401.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst401.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst401.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst401.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst401.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst401.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst401.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst401.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst401.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst401.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst401.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst401.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst401.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1046.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1046.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1046.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1046.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1046.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1046.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1046.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1046.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1046.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1046.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1046.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1046.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1046.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1046.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1046.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1046.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1046.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1046.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1046.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1046.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1046.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1046.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1046.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1046.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1046.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1046.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1046.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1046.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1046.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1046.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1046.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1046.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1046.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1394.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1394.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1394.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1394.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1394.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1394.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1394.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1394.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1394.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1394.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1394.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1394.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1394.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1394.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1394.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1394.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1394.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1394.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1394.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1394.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1394.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1394.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1394.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1394.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1394.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1394.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1394.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1394.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1394.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1394.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1394.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1394.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1394.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1629.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1629.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1629.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1629.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1629.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1629.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1629.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1629.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1629.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1629.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1629.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1629.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1629.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1629.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1629.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1629.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1629.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1629.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1629.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1629.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1629.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1629.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1629.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1629.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1629.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1629.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1629.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1629.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1629.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1629.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1629.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1629.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1629.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1862.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1862.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1862.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1862.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1862.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1862.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1862.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1862.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1862.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1862.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1862.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1862.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1862.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1862.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1862.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1862.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1862.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1862.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1862.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1862.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1862.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1862.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1862.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1862.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1862.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1862.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1862.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1862.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1862.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1862.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1862.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1862.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1862.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2210.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2210.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2210.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2210.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2210.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2210.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2210.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2210.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2210.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2210.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2210.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2210.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2210.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2210.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2210.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2210.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2210.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2210.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2210.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2210.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2210.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2210.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2210.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2210.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2210.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2210.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2210.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2210.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2210.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2210.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2210.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2210.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2210.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2250.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2250.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2250.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2250.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2250.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2250.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2250.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2250.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2250.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2250.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2250.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2250.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2250.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2250.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2250.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2250.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2250.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2250.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2250.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2250.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2250.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2250.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2250.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2250.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2250.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2250.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2250.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2250.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2250.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2250.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2250.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2250.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2250.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2461.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2461.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2461.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2461.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2461.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2461.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2461.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2461.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2461.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2461.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2461.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2461.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2461.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2461.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2461.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2461.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2461.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2461.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2461.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2461.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2461.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2461.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2461.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2461.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2461.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2461.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2461.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2461.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2461.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2461.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2461.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2461.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2461.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2711.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2711.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2711.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2711.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2711.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2711.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2711.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2711.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2711.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2711.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2711.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2711.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2711.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2711.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2711.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2711.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2711.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2711.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2711.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2711.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2711.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2711.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2711.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2711.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2711.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2711.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2711.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2711.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2711.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2711.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2711.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2711.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2711.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2731.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2731.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2731.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2731.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2731.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2731.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2731.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2731.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2731.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2731.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2731.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2731.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2731.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2731.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2731.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2731.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2731.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2731.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2731.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2731.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2731.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2731.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2731.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2731.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2731.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2731.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2731.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2731.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2731.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2731.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2731.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2731.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2731.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3889.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3889.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3889.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3889.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3889.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3889.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3889.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3889.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3889.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3889.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3889.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3889.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3889.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3889.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3889.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3889.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3889.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3889.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3889.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3889.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3889.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3889.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3889.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3889.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3889.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3889.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3889.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3889.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3889.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3889.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3889.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3889.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3889.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4378.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4378.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4378.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4378.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4378.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4378.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4378.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4378.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4378.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4378.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4378.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4378.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4378.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4378.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4378.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4378.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4378.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4378.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4378.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4378.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4378.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4378.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4378.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4378.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4378.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4378.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4378.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4378.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4378.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4378.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4378.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4378.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4378.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4426.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4426.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4426.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4426.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4426.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4426.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4426.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4426.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4426.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4426.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4426.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4426.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4426.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4426.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4426.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4426.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4426.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4426.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4426.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4426.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4426.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4426.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4426.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4426.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4426.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4426.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4426.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4426.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4426.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4426.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4426.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4426.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4426.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4977.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4977.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4977.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4977.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4977.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4977.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4977.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4977.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4977.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4977.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4977.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4977.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4977.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4977.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4977.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4977.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4977.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4977.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4977.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4977.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4977.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4977.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4977.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4977.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4977.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4977.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4977.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4977.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4977.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4977.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4977.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4977.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4977.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5226.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5226.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5226.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5226.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5226.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5226.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5226.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5226.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5226.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5226.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5226.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5226.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5226.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5226.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5226.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5226.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5226.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5226.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5226.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5226.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5226.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5226.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5226.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5226.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5226.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5226.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5226.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5226.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5226.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5226.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5226.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5226.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5226.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5524.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5524.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5524.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5524.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5524.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5524.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5524.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5524.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5524.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5524.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5524.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5524.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5524.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5524.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5524.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5524.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5524.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5524.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5524.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5524.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5524.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5524.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5524.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5524.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5524.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5524.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5524.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5524.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5524.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5524.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5524.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5524.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5524.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5707.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5707.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5707.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5707.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5707.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5707.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5707.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5707.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5707.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5707.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5707.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5707.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5707.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5707.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5707.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5707.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5707.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5707.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5707.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5707.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5707.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5707.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5707.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5707.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5707.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5707.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5707.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5707.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5707.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5707.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5707.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5707.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5707.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5931.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5931.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5931.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5931.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5931.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5931.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5931.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5931.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5931.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5931.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5931.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5931.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5931.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5931.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5931.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5931.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5931.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5931.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5931.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5931.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5931.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5931.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5931.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5931.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5931.xdly.x1i120 4.17 0.00 12.50 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5931.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5931.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5931.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5931.xdly.x1i175 8.33 0.00 25.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5931.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5931.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5931.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5931.xdly.xfc.x3 45.83 50.00 37.50 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5992.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5992.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5992.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5992.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5992.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5992.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5992.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5992.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5992.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5992.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5992.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5992.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5992.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5992.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5992.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5992.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5992.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5992.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5992.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5992.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5992.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5992.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5992.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5992.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5992.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5992.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5992.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5992.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5992.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5992.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5992.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5992.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5992.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6070.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6070.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6070.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6070.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6070.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6070.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6070.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6070.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6070.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6070.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6070.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6070.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6070.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6070.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6070.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6070.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6070.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6070.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6070.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6070.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6070.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6070.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6070.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6070.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6070.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6070.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6070.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6070.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6070.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6070.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6070.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6070.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6070.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6198.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6198.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6198.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6198.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6198.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6198.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6198.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6198.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6198.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6198.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6198.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6198.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6198.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6198.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6198.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6198.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6198.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6198.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6198.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6198.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6198.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6198.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6198.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6198.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6198.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6198.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6198.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6198.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6198.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6198.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6198.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6198.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6198.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6411.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6411.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6411.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6411.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6411.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6411.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6411.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6411.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6411.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6411.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6411.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6411.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6411.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6411.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6411.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6411.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6411.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6411.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6411.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6411.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6411.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6411.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6411.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6411.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6411.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6411.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6411.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6411.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6411.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6411.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6411.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6411.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6411.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6742.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6742.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6742.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6742.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6742.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6742.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6742.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6742.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6742.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6742.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6742.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6742.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6742.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6742.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6742.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6742.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6742.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6742.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6742.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6742.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6742.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6742.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6742.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6742.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6742.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6742.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6742.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6742.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6742.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6742.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6742.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6742.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6742.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7211.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7211.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7211.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7211.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7211.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7211.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7211.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7211.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7211.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7211.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7211.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7211.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7211.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7211.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7211.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7211.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7211.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7211.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7211.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7211.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7211.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7211.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7211.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7211.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7211.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7211.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7211.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7211.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7211.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7211.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7211.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7211.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7211.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7238.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7238.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7238.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7238.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7238.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7238.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7238.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7238.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7238.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7238.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7238.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7238.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7238.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7238.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7238.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7238.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7238.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7238.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7238.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7238.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7238.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7238.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7238.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7238.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7238.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7238.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7238.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7238.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7238.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7238.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7238.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7238.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7238.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7340.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7340.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7340.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7340.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7340.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7340.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7340.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7340.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7340.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7340.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7340.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7340.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7340.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7340.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7340.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7340.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7340.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7340.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7340.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7340.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7340.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7340.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7340.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7340.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7340.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7340.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7340.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7340.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7340.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7340.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7340.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7340.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7340.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7653.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7653.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7653.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7653.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7653.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7653.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7653.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7653.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7653.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7653.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7653.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7653.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7653.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7653.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7653.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7653.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7653.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7653.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7653.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7653.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7653.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7653.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7653.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7653.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7653.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7653.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7653.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7653.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7653.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7653.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7653.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7653.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7653.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7801.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7801.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7801.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7801.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7801.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7801.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7801.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7801.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7801.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7801.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7801.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7801.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7801.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7801.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7801.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7801.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7801.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7801.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7801.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7801.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7801.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7801.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7801.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7801.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7801.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7801.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7801.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7801.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7801.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7801.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7801.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7801.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7801.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7986.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7986.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7986.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7986.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7986.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7986.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7986.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7986.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7986.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7986.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7986.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7986.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7986.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7986.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7986.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7986.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7986.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7986.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7986.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7986.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7986.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7986.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7986.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7986.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7986.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7986.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7986.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7986.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7986.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7986.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7986.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7986.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7986.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8251.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8251.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8251.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8251.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8251.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8251.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8251.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8251.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8251.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8251.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8251.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8251.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8251.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8251.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8251.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8251.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8251.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8251.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8251.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8251.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8251.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8251.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8251.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8251.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8251.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8251.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8251.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8251.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8251.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8251.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8251.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8251.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8251.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9148.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9148.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9148.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9148.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9148.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9148.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9148.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9148.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9148.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9148.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9148.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9148.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9148.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9148.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9148.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9148.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9148.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9148.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9148.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9148.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9148.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9148.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9148.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9148.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9148.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9148.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9148.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9148.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9148.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9148.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9148.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9148.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9148.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9164.xdly.x1i27 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9164.xdly.x1i28 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9164.xdly.x1i29 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9164.xdly.x1i30 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9164.xdly.x1i31 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9164.xdly.x1i36 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9164.xdly.x1i40 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9164.xdly.x1i45 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9164.xdly.x1i49 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9164.xdly.x1i50 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9164.xdly.x1i51 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9164.xdly.x1i80 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9164.xdly.x1i81 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9164.xdly.x1i82 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9164.xdly.x1i83 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9164.xdly.x1i84 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9164.xdly.x1i85 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9164.xdly.x1i89 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9164.xdly.x1i93 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9164.xdly.x1i96 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9164.xdly.x1i103 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9164.xdly.x1i108 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9164.xdly.x1i112 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9164.xdly.x1i117 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9164.xdly.x1i120 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9164.xdly.x1i121 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9164.xdly.x1i122 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9164.xdly.x1i123 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9164.xdly.x1i175 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9164.xdly.x1i177 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9164.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9164.xdly.x1i193 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9164.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9178.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9178.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9178.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9178.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9178.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9178.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9178.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9178.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9178.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9178.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9178.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9178.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9178.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9178.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9178.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9178.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9178.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9178.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9178.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9178.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9178.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9178.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9178.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9178.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9178.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9178.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9178.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9178.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9178.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9178.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9178.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9178.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9178.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9403.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9403.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9403.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9403.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9403.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9403.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9403.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9403.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9403.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9403.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9403.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9403.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9403.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9403.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9403.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9403.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9403.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9403.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9403.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9403.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9403.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9403.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9403.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9403.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9403.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9403.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9403.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9403.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9403.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9403.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9403.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9403.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9403.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9425.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9425.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9425.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9425.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9425.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9425.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9425.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9425.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9425.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9425.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9425.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9425.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9425.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9425.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9425.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9425.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9425.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9425.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9425.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9425.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9425.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9425.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9425.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9425.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9425.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9425.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9425.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9425.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9425.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9425.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9425.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9425.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9425.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9788.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9788.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9788.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9788.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9788.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9788.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9788.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9788.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9788.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9788.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9788.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9788.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9788.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9788.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9788.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9788.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9788.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9788.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9788.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9788.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9788.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9788.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9788.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9788.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9788.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9788.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9788.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9788.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9788.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9788.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9788.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9788.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9788.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9915.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9915.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9915.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9915.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9915.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9915.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9915.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9915.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9915.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9915.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9915.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9915.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9915.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9915.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9915.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9915.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9915.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9915.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9915.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9915.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9915.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9915.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9915.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9915.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9915.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9915.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9915.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9915.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9915.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9915.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9915.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9915.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9915.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10217.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10217.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10217.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10217.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10217.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10217.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10217.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10217.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10217.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10217.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10217.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10217.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10217.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10217.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10217.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10217.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10217.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10217.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10217.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10217.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10217.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10217.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10217.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10217.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10217.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10217.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10217.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10217.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10217.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10217.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10217.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10217.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10217.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11361.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11361.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11361.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11361.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11361.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11361.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11361.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11361.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11361.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11361.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11361.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11361.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11361.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11361.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11361.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11361.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11361.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11361.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11361.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11361.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11361.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11361.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11361.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11361.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11361.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11361.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11361.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11361.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11361.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11361.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11361.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11361.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11361.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11605.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11605.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11605.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11605.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11605.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11605.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11605.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11605.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11605.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11605.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11605.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11605.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11605.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11605.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11605.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11605.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11605.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11605.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11605.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11605.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11605.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11605.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11605.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11605.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11605.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11605.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11605.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11605.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11605.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11605.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11605.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11605.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11605.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11664.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11664.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11664.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11664.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11664.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11664.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11664.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11664.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11664.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11664.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11664.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11664.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11664.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11664.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11664.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11664.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11664.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11664.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11664.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11664.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11664.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11664.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11664.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11664.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11664.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11664.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11664.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11664.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11664.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11664.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11664.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11664.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11664.xdly.xfc.x3 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11943.xdly.x1i27 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11943.xdly.x1i28 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11943.xdly.x1i29 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11943.xdly.x1i30 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11943.xdly.x1i31 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11943.xdly.x1i36 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11943.xdly.x1i40 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11943.xdly.x1i45 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11943.xdly.x1i49 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11943.xdly.x1i50 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11943.xdly.x1i51 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11943.xdly.x1i80 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11943.xdly.x1i81 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11943.xdly.x1i82 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11943.xdly.x1i83 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11943.xdly.x1i84 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11943.xdly.x1i85 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11943.xdly.x1i89 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11943.xdly.x1i93 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11943.xdly.x1i96 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11943.xdly.x1i103 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11943.xdly.x1i108 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11943.xdly.x1i112 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11943.xdly.x1i117 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11943.xdly.x1i120 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11943.xdly.x1i121 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11943.xdly.x1i122 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11943.xdly.x1i123 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11943.xdly.x1i175 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11943.xdly.x1i177 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11943.xdly.x1i187 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11943.xdly.x1i193 0.00 0.00 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11943.xdly.xfc.x3 33.33 50.00 0.00 50.00

Cond Coverage for Module : tm28hpcp_dlyc_d4_l35
TotalCoveredPercent
Conditions2150.00
Logical2150.00
Non-Logical00
Event00

 LINE       10
 EXPRESSION (EN ? ((~IN2X)) : IN)
             -1
-1-Status
0Covered
1Not Covered

Toggle Coverage for Module : tm28hpcp_dlyc_d4_l35
TotalCoveredPercent
Totals 8 4 50.00
Total Bits 16 8 50.00
Total Bits 0->1 8 4 50.00
Total Bits 1->0 8 4 50.00

Ports 8 4 50.00
Port Bits 16 8 50.00
Port Bits 0->1 8 4 50.00
Port Bits 1->0 8 4 50.00

Port Details
NameToggleToggle 1->0Toggle 0->1Direction
IN Yes Yes Yes INPUT
IN2X Yes Yes Yes INPUT
EN No No No INPUT
ENP No No No INPUT
OUT Yes Yes Yes OUTPUT
INX Yes Yes Yes OUTPUT
VDD No No No INPUT
VSS No No No INPUT


Branch Coverage for Module : tm28hpcp_dlyc_d4_l35
Line No.TotalCoveredPercent
Branches 2 1 50.00
TERNARY 10 2 1 50.00


10 assign OUT = EN ? ~IN2X : IN; -1- ==> ==>

Branches:
-1-Status
1 Not Covered
0 Covered

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%